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이일완,채수익 대한전자공학회 1994 전자공학회논문지-A Vol.31 No.6
Stochastic computation is adopted to reduce the silicon area of the multipliers in implementing neural network in VLSI. In addition to this advantage, the stochastic computation has inherent random errors which is required for implementing Boltzmann machine. This random noise is useful for the simulated annealing which is employed to achieve the global minimum for the Boltzmann Machine. In this paper, we propose a method to implement the Boltzmann machine with stochastic computation and discuss the addition problem in stochastic computation and its simulated annealing in detail. According to this analysis Boltzmann machine using stochastic computation is suitable for the pattern recognition/completion problems. We have verified these results through the simulations for XOR, full adder and digit recognition problems, which are typical of the pattern recognition/completion problems.
거리 근사를 이용하는 고속 최근 이웃 탐색 분류기에 관한 연구
이일완,채수익 대한전자공학회 1997 電子工學會論文誌, C Vol.c34 No.2
In this paper, we propose a new nearest-neighbor classifier with reduced computational complexity in search process. In the proposed classifier, the classes are divided into two sets: reference and non-reference sets. It reduces computational requriement by approximating the distance between the input and a class iwth the information of distances among the calsses. It calculates only the distance between the input and the reference classes. We convert a given classifier into RCC (reduced computational complexity but smal lincrease in misclassification probability of its corresponding RCC classifier. We designed RCC classifiers for the recognition of digits from the NIST database. We obtained an RCC classifier with 60% reduction in the computational complexity with the cost of 0.5% increase in misclassification probability.
김정민,홍석균,이일완,채수익 대한전자공학회 1996 전자공학회논문지-A Vol.33 No.5
The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.