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      • LDI용 1T 구조의 그래픽메모리 제어회로 설계

        이보선 ( Bo Sun Lee ),최호용 ( Ho Yong Choi ) 충북대학교 산업과학기술연구소 2011 산업과학기술연구 논문집 Vol.25 No.2

        In this paper, we have designed a control circuit of 1T graphic memory for LDI which iscapable of changing a refresh clock by setting a clock register to adjust process variations or frame frequency variations, and the memory design can be designed with minimum cell size. The main circuit consists of a reference clock generator which generates a reference clock determined by the size of optimal memory cell, a frame frequency clock generator which generates a frame clock by user setting, and a self refresh control block in which a refresh clock is generated by comparing the reference clock to the frame frequency clock. The proposed control circuit has been designed in transistor level using 0.18㎛CMOS technology library. Simulation results show that the frame clock frequency has 8.5Hz ~ 132Hz and refresh operation of 1T is well performed with even the memory cell size as small as 12fF at the frame clock frequency 60Hz.

      • KCI등재

        직장인의 생활체육 참여가 직무스트레스 및 삶의 질에 미치는 영향

        이보선(Lee Bo Sun),성영호(Seoung Young Ho),오준석(Oh Joon Suhk) 한국사회체육학회 2000 한국사회체육학회지 Vol.14 No.-

        The purpose of this study is to identify the effects of participation in practical sport for office workers on job stress and quality of life. To achieve the aim, this study is to analyze firstly the difference of job stress and life quality depends on the properties of office workers in terms of social demography, secondly the difference of job stress and life quality depends on participation extent in practical sport, thirdly the effect of participation extent in practical sport on job stress and life quality, and fourthly casual relationship between participation in practical sports and job stress or life quality. Set up office workers who are working at company located in Kyounggi - do as population, and then analyzed 334 participants in sport and 383 non-participants based on systematic cluster sampling. A tool to investigate, questionnaire was composed by total 58 questions such as 11 questions on demographic properties, 18 questions on job stress, 24 questions on leisure satisfaction, 5 questions on life satisfaction. Frequency Analysis, T-Test and One - Way ANOVA, ANCOVA and Multiple Regression Analysis were applied to analyze the collected data in accordance with the purpose of this study. Follows are results through data analysis in accordance with the above method and procedure. The first, showed a meaningful difference 0.196 in age, education level, position, working year, family's income and difference 59o in level and sex among the variables of job stress. In addition, the sub-variables of life quality are leisure satisfaction and life satisfaction, and leisure satisfaction showed a meaningful difference 5% in education level and family's income, and life satisfaction showed a meaningful difference l% in education level and 0.1% in age, position and family's income. The second, job stress and life quality depends on the participation in practical sport showed a meaningful difference 0.1% in the only life satisfaction that is a sub-variable of life quality. Non-participation group in practical sport showed a high degree in job stress but a low degree in leisure satisfaction and life satisfaction. The third, two elements of participation extent in practical sport did not influence upon job stress, and the only frequency of two elements influenced statically upon leisure satisfaction and life satisfaction as 1% respectively. The fourth, leisure satisfaction 6.496, job stress 9.5Zo and participation frequency 11.2Zo explained independently about life satisfaction, and the applied independent variables explained 12.6Fo of whole variables related with life satisfaction. The relation on life satisfaction showed a relative high degree in the period and frequency of participation, the whole effect of leisure satisfaction and showed a low degree in job stress.

      • KCI등재
      • KCI등재

        가산기와 MIPS CPU 사례를 이용한 현대 FPGA의 특성연구

        이보선(Bo Seon Lee),서태원(Tae Won Suh) 한국컴퓨터교육학회 2013 컴퓨터교육학회 논문지 Vol.16 No.3

        ASIC설계에서 FPGA를 이용한 에뮬레이션은 설계 검증을 위한 필수 단계이다. ASIC으로 설계된 모델을 가능한 최대 동작주파수로 에뮬레이션하기 위해서는 FPGA의 특성을 이해해야 한다. 본 논문은 FPGA의 주요 제조사인 Xilinx와 Altera의 여러 디바이스에 다양한 가산기와 MIPS CPU를 포팅하여, 디자인 복잡도에 따른 현대 FPGA의 특성을 연구하였다. 실험 결과, 일반적인 통념과는 다르게 1-bit 가산기를 기반으로 디자인한 RCA는 FPGA 내부의 carry-chain을 활용하지 못했고, 그 결과 다른 타입의 가산기보다 낮은 성능을 보였다. 또한, 본 연구를 통해 Xilinx와 Altera 제조사 별 FPGA 특성에 확연한 차이가 있음을 확인하였다. 즉, 동작속도에 최적화하여 설계된 Prefix 가산기를 Xilinx 디바이스에 포팅했을 때 저조한 동작주파수를 보였으나, Altera 디바이스에서는 IP Core와 비슷한 성능을 보였다. 이는 Altera 디바이스에서는 FPGA의 면적만 허락한다면 ASIC에 최적화된 설계를 그대로 사용하여도 에뮬레이션 성능에 영향을 미치지 않음을 시사한다. MIPS CPU를 통한 실험은 이를 뒷받침한다. The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

      • KCI등재

        소아천식 환자에서 충격진동법과 폐활량기로 측정한 소기도 장애와 호기산화질소와의 관계

        보선 ( Bo Seon Seo ),이정민 ( Jeong Min Lee ),조은혜 ( Eunhae Cho ),백지현 ( Ji Hyeon Baek ),이경석 ( Geong Suk Lee ),신윤호 ( Youn Ho Shin ),지혜미 ( Hye Mi Jee ),정영호 ( Yong Ho Jung ),한만용 ( Man Yong Han ) 대한천식알레르기학회 2015 Allergy Asthma & Respiratory Disease Vol.3 No.4

        Purpose: Fractional exhaled nitric oxide (FeNO) is a maker of airway inflammation, and impedance of low frequency in the impulse oscillometry system (IOS) reflects small-airway obstruction. We investigated the association of the FeNO level with IOS parameters and spirometry results in asthma patients. Methods: Fifty-eight children with asthma (60.3%, male), mean age 8.3 years (range, 4.5.16.0 years), were enrolled in the study. Reactance and resistance at 5 Hz with IOS, forced expiratory volume in one second (FEV1), forced vital capacity (FVC), and forced expiratory flow 25%.75% of the vital capacity (FEF25%-75%) with spirometry and FeNO were measured in all patients. The Z-score of spirometry and IOS parameters and the mean level of FeNO were used for correlation and regression analysis. Results: FeNO was not significantly associated with height, age, or other demographic parameters. There was a statistically significant correlation between spirometry results and IOS measurements. The FeNO level was not significantly correlated with IOS variables. After adjusting for height, sex, atopic status, and the use of inhaled corticosteroid, the FeNO level showed significant correlations with Z-score of FEV1/FVC (P=0.037, adjusted R2=0.234). Conclusion: FeNO was significantly correlated with Z-scores of FEV1/FVC, but not with IOS variables. Therefore, FeNO may be used to detect whole airway obstruction, but not small-airway obstruction. (Allergy Asthma Respir Dis 2015;3:267-271)

      • KCI등재

        컴퓨터과학 : 가산기와 MIPS CPU 사례를 이용한 현대 FPGA의 특성연구

        이보선 ( Bo Seon Lee ),서태원 ( Tae Won Suh ) 한국컴퓨터교육학회 2013 컴퓨터교육학회 논문지 Vol.16 No.3

        ASIC설계에서 FPGA를 이용한 에뮬레이션은 설계 검증을 위한 필수 단계이다. ASIC으로 설계된 모델을 가능한 최대 동작주파수로 에뮬레이션하기 위해서는 FPGA의 특성을 이해해야 한다. 본 논문은 FPGA의 주요 제조사인 Xilinx와 Altera의 여러 디바이스에 다양한 가산기와 MIPS CPU를 포팅하여, 디자인 복잡도에 따른 현대 FPGA의 특성을 연구하였다. 실험 결과, 일반적인 통념과는 다르게 1-bit 가산기를 기반으로 디자인한 RCA는 FPGA 내부의 carry-chain을 활용하지 못했고, 그 결과 다른 타입의 가산기보다 낮은 성능을 보였다. 또한, 본 연구를 통해 Xilinx와 Altera 제조사 별 FPGA 특성에 확연한 차이가 있음을 확인하였다. 즉, 동작속도에 최적화하여 설계된 Prefix 가산기를 Xilinx 디바이스에 포팅했을 때 저조한 동작주파수를 보였으나, Altera 디바이스에서는 IP Core와 비슷한 성능을 보였다. 이는 Altera 디바이스에서는 FPGA의 면적만 허락한다면 ASIC에 최적화된 설계를 그대로 사용하여도 에뮬레이션 성능에 영향을 미치지 않음을 시사한다. MIPS CPU를 통한 실험은 이를 뒷받침한다 The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

      • KCI등재

        컴퓨터과학 : PARSEC을 이용한 TILE-Gx36 다중코어 프로세서의 성능 평가 및 분석

        이보선 ( Bo Seon Lee ),김한이 ( Han Yee Kim ),유헌창 ( Heon Chang Yu ),서태원 ( Tae Weon Suh ) 한국컴퓨터교육학회 2014 컴퓨터교육학회 논문지 Vol.17 No.1

        본 논문은 다중코어의 성능을 평가하고 분석하기 위해 TILE-Gx36(Gx36) 다중코어 프로세서를 사례로 연구하였다. Gx36의 성능 평가는 비교적 최신 병렬 벤치마크인 PARSEC을 이용하였고, 성능 분석을 돕기 위한 비교 시스템으로 인텔의 Core i7 (i7)과 Atom을 사용하였다. 실험결과 2의 제곱으로 동시에 수행 가능한 스레드를 발생시켰을 때, Gx36은 i7보다 평균 2.73배 낮은 성능을 보였으며, Atom보다는 평균 1.93배 높은 성능을 보였다. Gx36은 비교 프로세서보다 상대적으로 큰 Last-Level Cache(LLC)를갖고 있음에도 불구하고, 가장 많은 LLC miss를 발생시켰다. 이는 Gx36이 기대치 이하의 성능을 보이는 주된 이유로 판단되며, DDC가 일반적 고성능 컴퓨팅을 위한 캐시구조로 적절하지 않음을 보여준다.다중코어 시스템의 실측을 통한 성능평가는 향후 다중코어 구조개선 및 올바른 방향 설정을 위한 객관적인 자료를 제공한다. This paper evaluates and analyzes the performance of TILE-Gx36(Gx36), a many-core processor. The PARSEC parallel benchmark suite was used to measure the performance, and Core i7 (i7) and Atom are used for the performance comparison. When experimented with the maximum number of threads that can be executed concurrently on each machine, Gx36 showed a 2.73×inferior performance to Core i7 and a 1.93× superior performance to Atom. Gx36 has the largest Last Level Cache(LLC) among the compared processors. Nevertheless, it reported the biggest number of LLC misses, which, we strongly believe, is the major culprit for lower performance than expected. Our study suggests that the DDC employed in Gx36 is not a favorable cache structure for the general-purpose high-performance computing. The actual measurement with off-the-shelf machine provides non-biased data for polishing the future many-core architecture.

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