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Low Complexity Systolic Montgomery Multiplication over Finite Fields GF(2m)
이건직 (사)디지털산업정보학회 2022 디지털산업정보학회논문지 Vol.18 No.1
Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.
Resource and Delay Efficient Polynomial Multiplier over Finite Fields GF (2m)
이건직 (사)디지털산업정보학회 2020 디지털산업정보학회논문지 Vol.16 No.2
Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.
이건직 (사)디지털산업정보학회 2020 디지털산업정보학회논문지 Vol.16 No.4
SCADA (Supervisory Control and Data Acquisition) systems for remote monitoring, data acquisition and control are applied to major industrial infrastructures including power, water and railroad. Recently, there are many researches on key management scheme for secure communication due to change to the open network environment. These systems are located at far distances and are connected to the main control center through various types of communication methods. Due to the nature of these systems, they are becoming the significant targets of cyber attack. We propose an efficient key management scheme which is established on ID-based cryptosystem without an expensive computation on MTU (Master Terminal Unit), Sub-MTU, and RTU (Remote Terminal Unit). The proposed method is secure and effective in key management among multiple legitimate devices.
고속 모듈러 지수연산을 위한 모듈러 곱셈기의 선형 시스톨릭 어레이 설계
이건직(Keon-Jik Lee),허영준(Young-Jun Heo),유기영(Kee-Young Yoo) 한국정보과학회 1999 정보과학회논문지 : 시스템 및 이론 Vol.26 No.9
공개키 암호화 시스템에서 주된 연산은 512비트 이상의 큰 수에 의한 모듈러 지수 연산으로 표현되며, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 설계된 시스톨릭 어레이는 VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드나 smart 카드에 이용될 수 있다. The main operation of the public-key cryptographic system is represented the modular exponentiation containing 512 or more bits and computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery algorithm and design the linear systolic array for performing modular multiplication and modular squaring simultaneously using the computable part in common in right-to-left modular exponentiation. The systolic array presented in this paper could be designed on VLSI hardware and used in IC and smart card.
이건직(Keon-Jik Lee),허영준(Young-Jun Heo),유기영(Kee-Young Yoo) 한국정보과학회 1997 한국정보과학회 학술발표논문집 Vol.24 No.2Ⅳ
공개키 암호시스템에서 모듈러 지수 연산은 512비트 이상의 큰 수의 모듈러 곱셈 연산을 수행 하여야 한다. 내재된 모듈러 곱셈 횟수를 줄이기 위해 S(m)기법을 이용하여 지수를 S(m) 표현과 시스톨릭 S(m) 표현으로 변환하였다. 변환된 시스톨릭 S(m) 표현으로부터 모듈러 지수 연산을 위한 시스톨릭 어레이(systolic array)를 설계하였다.
이건직 ( Geon Jik Lee ),성진욱 ( Jin Uk Seong ),박주현 ( Ju Hyun Park ),조규수 ( Gyu Soo Joe ),박제철 ( Je Chul Park ) 한국환경과학회 2010 한국환경과학회지 Vol.19 No.7
This study was conducted to investigate runoff characteristics of non-point pollutants source at the urban area in boeun area, Chungbuk Province. The monitoring site covering the watershed of 2.11 km 2 contains about 40.3 % of total watershed with the urban area. The monitoring was conducted with six events for five months and Event Mean Concentration(EMC) and Site Mean Concentration(SMC) of SS, BOD, CODMn, T-N, T-P were calculated on the result of the water quality parameters. As a result of the comparion between Arithmetic Mean Concentration and Event Mean Concentration, it showed that over all Event Mean Concentration was higher than Arithmetic Mean Concentration. And it showed that SS, BOD, T-P featured the first-flushing effect, showing relatively high concentration in early-stage storm event.