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A Spread Spectrum Clock Generator for SATA II with Rounded Hershey-Kiss Modulation Profile
문용환,임완식,김태호,강진구,김이섭 한국전기전자학회 2011 전기전자학회논문지 Vol.15 No.2
A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using 0.18㎛ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10㏈. The active chip area is 0.36㎜ × 0.49㎜ and the chip consumes 30㎽ power at 1.5GHz.
RTS법을 이용한 연간 건물 냉난방 에너지 소비량 산정
문용환(Yong-Hwan Moon),성순경(Sun-Kyung Sung) 대한설비공학회 2016 대한설비공학회 학술발표대회논문집 Vol.2016 No.11
As one of the techniques to estimate cooling and heating loads, the RTS method is based on an assumption that heat gain repeats in a 24 hour cycle under the steady and periodic conditions. Therefore, the annual weather data of 8,760 hours used for calculation of hourly heat gain. Here, in order to consider the time lag effects, the conduction time series and radiant time series are used to distribute heat gain against time. If heat gain passes midnight in the distribution process, it can be expressed as the heat gain of the next day to calculate the consecutive loads by time period. Additionally, considering the properties of the partial operation load of the HVAC equipments, the study investigated whether the method can be used to estimate the annual energy usage. As a result, the annual heating and cooling energy usages estimated by the RTS method resulted in the differences of 1~2% from EnergyPlus and 8~24% from ECO2 for the respective systems of constant air and water volumes. For the system of variable air volume and that of variable water volume, the RTS method showed the differences of 0.5~4% from EnergyPlus and 3~15% from ECO2. Judging from the insignificant deviations from EnergyPlus, it was concluded that the RTS method can be practically used to evaluate the annual cooling and heating energy usages in buildings.
체세포배 (體細胞胚) 발생을 통한 콩 품종의 식물체 재분화
문용환(Yong Hwan Moon),김세규(Se Kyu Kim),최상봉(Sang Bong Choi),이광웅(Kwang Woong Lee) 한국식물학회 1994 Journal of Plant Biology Vol.37 No.3
Effective plant regeneration from immature cotyledons of soybean [Glycine max (L.) Merr.] cultivars was achieved via somatic embryogenesis. Somatic embryogenesis was performed with the cotyledons of immature embryos 14-20 d after flowering. Immature cotyledons of cv. Whangkeum were placed abaxial or adaxial side down on modified MS medium containing 20 mg/L 2,4-D. The greatest number of somatic embryos, 1.2 per cotyledon, was produced from those of 4.0-4.9 mm in length which had been placed abaxial side down. Among cvs. Pecking, Whangkeum and Baekwoon, Pecking had the highest embryo induction efficiency with 4.3 somatic embryos per cotyledon in 20 mg/L 2,4-D treatment and with 1.0 embryo per cotyledon in 8 mg/L NAA treatment. Germinable globular somatic embryos were induced with the highest efficiency, 27.6%, in 20 mg/L 2,4-D and were proliferated efficiently on liquid medium containing 10 mg/L 2,4-D. The globular somatic embryos developed into germinable mature somatic embryos on medium containing 10 μM CoCl_2, 9% sucrose, and 0.5% activated charcoal. These mature somatic embryos germinated on hormone-free medium. After transfer to the soil, regenerated plants with seeds were obtained.
진현배,문용환,장지훈,김태호,송병철,강진구,Jin, Hyun-Bae,Moon, Yong-Hwan,Jang, Ji-Hoon,Kim, Tae-Ho,Song, Byung-Cheol,Kang, Jin-Ku 한국전기전자학회 2011 전기전자학회논문지 Vol.15 No.2
본 논문은 디스플레이포트의 보조채널에서 고속 데이터 전송을 할 수 있는 고속 양방향 보조 채널을 구성하기 위한 새로운 송 수신기 구조를 제안하고 적용에 대해 서술하였다. 제안된 고속 보조 채널은 저속 전송에서 맨체스터 인코딩을 사용하여 1Mbps대역폭을, 고속 전송에서 8B/10B인코딩 방식을 사용하여 720Mbps의 대역폭을 지원한다. 맨체스터 전송을 사용하여 고속 보조채널 및 메인링크의 링크 서비스 및 디바이스 서비스를 위한 저속 보조채널 블록을 제안하고, 8B/10B인코딩 방식을 통하여 보조채널을 통한 고속 데이터 전송을 위한 블록을 제안한다. 또한 데이터 패킷 구조와 데이터 전송방식에 대하여 정의하였다. 설계된 시스템은 Verilog HDL로 설계 되었으며, 고속 보조채널 송 수신기는 Xilinx Vertex4 FPGA을 사용하여 합성한 결과 7,648개의 LUTs와 6,020개의 registers를 사용 하였으며, 최대 동작 속도는 203MHz의 성능을 확인 하였다. This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel transmitter and receiver are implemented with 7,648 LUTs and 6,020 slice register synthesized in Xilinx Vertex4 FPGA and can be operated at 72MHz to support 720Mbps.
A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
서진철,문용환,서준협,장재영,안택준,강진구 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.3
In this paper, a clock and data recovery(CDR) circuit that supports triple data rates of 1.62,2.7, and 5.4 Gbps for DisplayPort 1.2 standard isdescribed. The proposed CDR circuit covers threedifferent operating frequencies with a single VCOswitching the operating frequency by the 3-bit digitalcode. The prototype chip has been designed andverified using a 65 nm CMOS technology. Therecovered-clock jitter with the data rates of1.62/2.7/5.4 Gbps at 231-1 PRBS is measured to7/5.6/4.7 psrms, respectively, while consuming 11 mWfrom a 1.2 V supply.
A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile
오승욱,박형민,문용환,강진구 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
This paper describes a spread spectrumclock generator (SSCG) circuit for DisplayPort 1.2standard. A Hershey-Kiss modulation profile isgenerated by dual sigma-delta modulators. Thestructure generates various modulation slopes toshape a non-linear modulation profile. The proposedSSCG for DisplayPort 1.2 generates clock signals with5000 ppm down spreading with a Hershey-Kissmodulation profile at three different clock frequencies,540 MHz, 270 MHz and 162 MHz. The measuredpeak power reduction is about 15.6 dB at 540 MHzwith the chip fabricated using a 0.13 8m CMOStechnology.