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3-level Incremental Sigma-Delta ADC 설계
김혜인(Heain Kim),권기백(Kwon Kibaek),김면식(Kim Myunsik),손지원(Son jiwon),박상순(Park Sangsoon),최중호(Joongho Choi) 대한전자공학회 2021 대한전자공학회 학술대회 Vol.2021 No.6
A Incremental second-order sigma-delta ADC is presented. A method using a combination of a 1.5-bit Quantizer technique and DWE configuration enabled wide dynamic range operation. also A three-level Quantizer with simple dynamic element matching improve linearity. The prototype IC implemented in a 0.13㎛ CMOS process achieves 125dB SNDR in a 60Hz signal bandwidth, while consuming 192uW from a 1.2V supply. The prototype operates from 1.2V supply with minimal performance degradation.