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심재훈(Jae-Hoon Sim),강재석(Jae-Seok Kang),김현수(Hyean-Soo Kim),유수봉(Su-Bong Ryu),김종호(Jong-Ho Kim),강민섭(Min-Sup Kang) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
In this paper, we present the design of AES cipher processor based on Modified S-Box. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler are utilized. Also, the S-Boxes is designed by applying composite field arithmetic on GF(((2²)²)²) for further reducing the area of S-Boxes. The proposed AES cipher processor is coded in Veilog-HDL, and synthesized through the use of Xilinx ISE 14.7 tool. In order to verify the designed processor, timing simulation is also performed by using simulator, ModelSim 10.3.