실시간 2차원 디지털 신호처리를 위한 VLSI 구조

권희훈 한국통신학회 1992 정보와 통신 Vol.9 No.9

다수의 처리 장치가 실시간 실현에 필수적이라는 것이 많은 디지털 신호처리를 일정한 시간 내에 하기 위한 요구 조건이다. VLSI 기술이 발전함으로 많은 기능 장치로 구성된 컴퓨터 시스템을 설계하고, 실현하는 것이 가능하게 되었다. 일정한 시간내에 높은 처리 능력을 갖음으로서 디지털 신호처리에 응용할 수 있는 VLSI 구조를 연구하는데 데이터 통신의 요구량과 계산의 복잡성을 최소화 할 수 있는 알고리듬의 개발이 요구된다. 이 문제를 해결하는 방법으로 DLSI 시스템이나 적응 시스템을 모델로 하는 효과적인 알고리듬을 조사하고 , 이 알고리듬을 실현할 수 있는 VLSI구조와 연관된 멀티 프로세서 시스템을 개발하는데 본 연구의 목적이 있다. 본 연구에서는 실시간 2차원 신호처리를 할 수 있는 새로운 VLSI 구조를 제안했다. 이 VLSI 구조는 칩 내부에서 단일 처리 장치가 갖는 개념을 다수의 처리 장치를 사용하는 경우로 확장하였다. 이 VLSI 구조는 입력 데이타의 크기가 증가함에 따라서 복잡성과 입력당 계산의 수가 증가하지 않는다는 장점을 갖기 때문에 매우 큰 2차원 데이타를 실시간에 처리할 수 있다. The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

디지털 라이프 실현을 위한 디지털 홈 구축과 서비스

권희훈 충주대학교 학생생활연구소 2004 學生生活硏究 Vol.11 No.-

버퍼 크기에 따른 SR ARQ 기법의 정보 전송률 분석

권희훈,안병근 忠州大學校 2003 한국교통대학교 논문집 Vol.38 No.3

A New procedure for handing retransmission in a selective-repeat ARQ system is proposed in this paper. This procedure can operate with a receive buffer of minimal size, in addition it place a little computational load on the transmit and receive processors. The procedure is simple enough that its throughput can be calculated exactly. Analysis of this strategy show that 1) it yields higher throughput than earlier ARQ techniques, 2) its throughput differs a little from channel capacity, for modest receive bugger size, 3) throughput approaches channel capacity, as buffer size increases. The final chapter of the paper considers the performance of ARQ system on channels in which errors in bursts. It indicates that, error burstiness has a little effect on throughput on resonable good channels.

디지털 신호처리기를 이용한 모터의 역률개선

권희훈 忠州大學校 2009 한국교통대학교 논문집 Vol.44 No.-

The design of single phase power factor correction using a digital single processor is proposed in this paper. The digital single processor requires the A/D sampling values for line input voltage to realize the proposed power factor correction converter. The sampling values contain a high frequency noise and switching ripple due to switching noise. The A/D converter of digital single processor are started using the prediction algorithm. It is shown that the power factor is 0.99 at wide input voltage from the experiment results. The parameters and gains of PI controllers are controlled by serial communication. Also it is shown that the implemented power factor correction converter can achieve feasibility and the usefulness.

잡음에 강한 웨이브렛 편이 변조 시스템

권희훈 忠州大學校 2008 한국교통대학교 논문집 Vol.43 No.-

Frequency shift keying(FSK), phase shift keying(PSK) and amplitude shift keying(ASK) are widely used in the conventional digital communications method. In this paper, new robustious WSK(wavelet shift keying) system using scaling and wavelet function in the digital communication are proposed in this paper. Wavelet Transform consist of a low frequency and high frequency coefficient. When the input signal is one, if it finds the impulse response, the signal is separated from the scaling and wavelet function. The binary data which assigned the scaling function to 1, and wavelet to 0 is encoded by modulator. The proposed algorithm is a robustious-noise in digital communication system.

수신기의 잡음을 제거하기 위한 역 콤 필터

권희훈 忠州大學校 2012 한국교통대학교 논문집 Vol.47 No.-

A comb filter is a filter that extracts a set of isolated equally spaced frequencies from a signal. Also an inverse comb is a filter that removes a set of isolated equally spaced frequencies from a signal. The cascaded integrator comb filters are widely used in high speed wireless communication systems since they have multiplier less low-power structure. In this paper, an inverse comb filter is proposed to improve frequency response characteristics. We proposed filter which can improve stopband and passband characteristics simultaneously.

낮은 전력 소모를 갖는 다단 다중 율 필터의 구조

권희훈 한국교통대학교 2015 한국교통대학교 논문집 Vol.50 No.-

Wireless communications have enabled digital convergence between various wireless applications in consumer electronics fields. In order to realize this digital convergence, efficient approaches in sub-system design such as reduction of chip area and power consumption have been required. The CIC filters are widely used in high speed wireless communication systems since they can save the power consumption by designing multi-rate structure that separates multistage. The double-sharpened decimation filter employing a compensator improves the passband response of a CIC filter. Furthermore, double-sharpened decimation filter can be realized using polyphase decomposition. An efficient design and implementation of the multistage multi-rate filter using a distributed algorithm is proposed to reduced the hardware complexity and power consumption.

디지털신호처리기를 사용한 협대역 신호전력검출기 구현

권희훈 忠州大學校 2007 한국교통대학교 논문집 Vol.42 No.-

An analog filter based conventional power detector has poor performance due to frequency drift of carrier. Also, it is difficult to change an analog filter bandwidth according to changed bandwidth of transmitted signal. We proposed digital signal processor based signal power detector which is easy to change bandwidth of filter and to filter and to match shifted frequency of carrier to solve these difficulties. This paper presents narrow band communication signal power detector which are implementation digital signal processor for tracking control of mobile antenna system. The proposed signal power detector consists of a FFT function to measure frequency drift of carrier, a programmable filter bank function to limit of received signal bandwidth and a power calculation function to measure power of filtered signal in 12-bit linear scale. Test results of implemented signal power detector showed that it satisfied required function and performances.

효율적인 다단 다중 율 필터의 구조

권희훈 한국교통대학교 2016 한국교통대학교 논문집 Vol.51 No.-

The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. They have been required efficient approaches in sub-system design such as reduction of chip area and power consumption to realize digital convergence. We can save the power consumption by designing multi-rate structure that separates multistage. A filter structure is used to improve frequency response characteristics in decimation filter using CIC filters and half band filters. Also an efficient design and implementation of the multistage multi-rate filter using a distributed algorithm is proposed to reduced the hardware complexity and power consumption.

웨이브 디지털 필터의 동적범위 개선 ( Improvement of Dynamic Range in Wave Digital Filter )

권희훈,김명기 한국통신학회 1987 한국통신학회 학술대회논문집 Vol.6 No.1