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스케일링 및 데이터 보존을 위한 2단자 사이리스터 랜덤 액세스 메모리 (T-RAM) 특성 분석
김향우(Hyangwoo Kim),조현수(Hyeonsu Cho),최민근(Minkeun Choi),공병돈(Byoung Don Kong),백창기(Chang-Ki Baek) 대한전자공학회 2020 대한전자공학회 학술대회 Vol.2020 No.8
2 terminal thyristor random-access memory (T-RAM) is investigated in terms of doping concentrations in the storage region to improve scalability and data retention time. When doping concentrations of N and P storage region are equal to each other at 1018 cm-3, T-RAM exhibits the highest retention time of 100 msec. In addition, it is proposed how to set the standby voltage in an energy-effective way. This standby voltage allows steady data retention of T-RAM with femto-scale leakage current until the erase operation is applied. Consequently, the proposed guideline can give a pathway to realize 2 terminal T-RAM as a promising capacitor-less DRAM technology.
고신뢰성 데이터 유지 특성을 가진 3단자 사이리스터 랜덤 액세스 메모리
김향우(Hyangwoo Kim),조현수(Hyeonsu Cho),서명해(Myunghae Seo),이승호(Seungho Lee),공병돈(Byoung Don Kong),백창기(Chang-Ki Baek) 대한전자공학회 2021 대한전자공학회 학술대회 Vol.2021 No.6
Three-terminal thyristor random access memory(TRAM) is investigated in terms of gate-cathode voltage(VGC,ST) and anode-cathode voltage(VAC,ST) in the standby state to improve the retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.55 V shows the continuous retention capability without refresh operation with a low standby current of 0.13 pA. In addition, the proposed array operation scheme can effectively minimize operation disturbances on unselected cells. Consequently, the three-terminal TRAM with the proposed array operation provides excellent retention and high-reliable memory configurations comparable with or surpass DRAM.