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- 저자 : 金澈福(Chul-Bok Kim) (검색결과 5 건)
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REVERSE MOAT 식각 공정 유·무에 따른 STI-CMP 공정의 평탄화 특성
김철복,박성우,정소영,서용진 대불대학교 2001 論文集 Vol.7 No.1
Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying CMP process to shallow trench isolation (STI) structure in 0.18㎛ semiconductor device. The reverse moat process has been added to employ in STI-CMP. Thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process than these defects affect the device characteristics. In this work, the high selectivity slurry(HSS) was developed to perform the direct global planarization without reverse moat etch step, and the planarization characteristics of STI-CMP process with and without reverse moat etch step were studied.
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CMP 공정에서 결함밀도 감소를 위한 POU 슬러리 필터의 특성과 탈이온수의 고분사법에 의한 패드수명의 개선
박성우,김철복,정소영,서용진 대불대학교 2001 論文集 Vol.7 No.1
As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1 ㎛ in size, which could cause micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5 ㎛ point of use (POU) filter, which is depth-type filter and has 80% filtering efficiency for the 1.0 ㎛ size particle. In this paper, we have studied the relationship between defect generation and polished wafer counts to understand the exact efficiency of the slurry filtration, and to find out the appropriated pad usage. Our experimental results of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects, and it is impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate, and to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of depth type filter.
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서용진,박성우,김철복,정소용,이경진,김기욱,박창준 대불대학교 2002 大佛大學校大學院 硏究論文集 Vol.- No.1
As the device geometry shrinks to the deep submicron region, chemical mechanical polishing(CMP) planarization become a more essential technique of advanced ULSI process. Also, CMP process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric(ILD) layers and interconnections with free-defect. Especially, the complete global planarization of IMD, ILD and interconnections can be achieved only with the CMP process. However, as the IMD and ILD layer gets thinner, several problems were found in the CMP process. It does have various problems such as dishing effect, torn oxide defects and nitride residues in oxide. So, it leads to severe circuit failure, which affects yield. In this paper, we studied the characteristics of polishing pad, which can apply STI-CMP process for global planarization of multilevel interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was defected less than 2 on JR111 pad. Through the above result, we can select optimum polishing pad, so we can expect the improvement of throughput and device yield.
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CMP 공정의 재현성 확보를 위한 공정제어 범위의 결정
서용진,정소영,김철복,박성우,이경진,김기욱,박창준 대불대학교 2002 大佛大學校大學院 硏究論文集 Vol.- No.1
To achieve the ULSI goals of higher density and greater performance, STI(shallow trench isolation)-CMP(chemical mechanical polishing) process has been attracted. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between SiO2 and Si3N4 films for the purpose of process simplification and in-situ EPD(end point detection). However, STI-CMP process has various defects such as nitride residue, torn oxide and demage of silicon active region. Also, it was difficult to assure the suitable process margin in the STI-CMP process. To solve these problems, in this paper, we discussed to determine the control limit of process, which can entirely remove the oxide on nitride film from the most area of high density as reducing the damage of dense moat area and minimizing dishing effect in the large field area. We, also, evaluated the wafer-to-wafer thickness variation and the day-by-day reproducibility of STI-CMP process after repeatable tests.
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