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김재경 ( Jaekyung Kim ),안진희 ( Jinhee An ),윤여중 ( Yejoong Yun ),최기영 ( Kiyoung Choi ) 한국농업기계학회 2019 한국농업기계학회 학술발표논문집 Vol.24 No.1
기내배양된 사과묘를 건전한 대목으로 생산하기 위해 순화와 육묘과정이 필요하며 육묘시 환경조건에 의해 사과묘의 수세가 달라지므로 1차 순화가 완료된 사과묘의 적정육묘 온도를 규명하고자 실험을 수행하였다. 환경이 조절되는 챔버에서 주/야 온도를 각각 18/18, 23/18, 30/18°C로 3처리하여 20일간 육묘한후 배지 종류별 생존율을 조사하였고, 광도를 높여 육묘한 후 생육 조사하였다. 온도 영향을 받은 사과묘 생존율은 23/18°C에서 97.5%로 가장 높았으며, 18/18°C에서 95%, 30/18°C에서 84.2% 생존하였다. 묘장은 2.9~4.5cm, 엽수 9.8~11매, 엽면적 18.6~32.8㎠으로 순화 온도 23°C에서 가장 생육이 높았다. 20일간 온도 영향으로 순화된 묘를 환경이 조절된 온실로 이동하여 1주 간격으로 3주간 광도를 높여 재배하였을 때 사과 묘는 묘장 5.6~8.5cm, 엽수 11~16매, 경경 1.6~2.5mm로 증가하였으며, 23°C 처리구에서 생육이 가장 높았으나, 엽수와 SPAD 값은 온도 처리간 차이가 없었다. 1주 이후 300 PPFD에서 재배되었을 때 사과 엽색이 적색을 발현하기 시작하였으며, 18°C 처리에 비해 온도가 높았던 묘소질 일수록 적색 발현은 높았다. 순화 중 온도의 영향을 받은 사과 묘는 육묘 환경에서도 묘소질의 생육 차이가 나타나 순화 온도는 23°C가 적합하였다.
A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS
Jeon, Dongsuk,Dong, Qing,Kim, Yejoong,Wang, Xiaolong,Chen, Shuai,Yu, Hao,Blaauw, David,Sylvester, Dennis IEEE 2017 IEEE journal of solid-state circuits Vol.52 No.6
<P>This paper presents an energy-efficient face detection and recognition processor aimed at mobile applications. The algorithmic optimizations including hybrid search scheme for face detection significantly reduce computational complexity and architecture modification such as feature memory segmentation and further reduce energy consumption. We utilize characteristics of the implemented algorithm and propose a 5T SRAM design heavily optimized for mostly-read operations. Systematic reset and write schemes allow for reliable data write operation. The 5T SRAM reduces the cell area by 7.2% compared to a conventional 6T bit cell in logic rule while significantly improving read margin and voltage scalability due to a decoupled read path. The fabricated processor consumes only 23 mW while processing both face detection and recognition in real time at 5.5 frames/s throughput.</P>
A Wire-overhead-free Reset Propagation Scheme for Millimeter-scale Sensor Systems
Inhee Lee,Suyoung Bang,Yejoong Kim,Gyouho Kim,Dennis Sylvester,David Blaauw,Yoonmyung Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.4
This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a 180-μm CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.
A Wire-overhead-free Reset Propagation Scheme for Millimeter-scale Sensor Systems
Lee, Inhee,Bang, Suyoung,Kim, Yejoong,Kim, Gyouho,Sylvester, Dennis,Blaauw, David,Lee, Yoonmyung The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.4
This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a $180-{\mu}m$ CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.
MBus: A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems
Lee, Inhee,Kuo, Ye-Sheng,Pannuto, Pat,Kim, Gyouho,Foo, Zhiyoong,Kempke, Ben,Jeong, Seokhyeon,Kim, Yejoong,Dutta, Prabal,Blaauw, David,Lee, Yoonmyung The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.6
This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.
MBus : A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems
Inhee Lee,Ye-Sheng Kuo,Pat Pannuto,Gyouho Kim,Zhiyoong Foo,Ben Kempke,Seokhyeon Jeong,Yejoong Kim,Prabal Dutta,David Blaauw,Yoonmyung Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.6
This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.