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Sub 1-V Operating Bootstrapped Latched CMOS Logic Families for Ultra Low-Voltage Application
Kong, Bai-Sun 한국항공대학교 2000 論文集 Vol.38 No.-
본 논문은 bootstrapped latched CMOS logic (BLCL)으로 통칭되는 몇 가지 새로운 저전압용 CMOS logic family를 제안한다. 이들 회로는 하나의 bootstrap capacitor만을 이용하여 내부 node의 전압을 supply voltage 이상으로 승압시켜 driver transistor의 구동 능력을 키움으로써 large capacitive load를 구동하는 경우에 속도 향상을 꾀할 수 있다. 또한, 제안된 demand-on boosting bootstrapped latched CMOS logic (DB-BLCL) 및 conditional-discharging bootstrapped latched CMOS logic (CD-BLCL) 회로의 각 bootstrap node는 승압 동작이 필요한 경우에만 bootstrapping 동작을 행하므로 전력 소모를 통계적으로 줄일 수 있고, driver transistor의 overdriving 구간이 출력 신호의 transition period로 제한되므로 gate-oxide stress를 최소화 할 수 있다. 이들 회로들을 0.35um CMOS process technology를 이용하여 설계하였으며, 모사 실험 결과 제안된 회로들은 기존의 회로에 비하여 약 33 - 59%의 전력 감소와 더불어 15 - 42%의 latency 감소 효과를 나타내었다. 또한, 최상의 조건에서는 전력 소모를 약 88% 까지 절감할 수 있음을 알 수 있었다. A set of novel low-voltage CMOS logic families, collectively called bootstrapped latched CMOS logic (BLCL), is proposed and analyzed. These circuits improve operation speed for driving a large capacitive load by boosting internal nodes using a single bootstrap capacitor. Each bootstrap node of DB-BLCL and CD-BLCL is boosted on demand to minimize power consumption, and the driver transistors are transiently overdriven during the transition period to minimize gate-oxide stress. These circuits were designed and fabricated using 0.35um CMOS process technology. The comparison result indicates that the proposed logic families achieve 33 ~ 59% reduction on power consumption with 15~42% reduced latency as compared to conventional CMOS circuits at sub-l V power supply region.
A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination
Sua Kim,Bai-Sun Kong,Chilgee Lee,Changhyun Kim,Young-Hyun Jun 한국전자통신연구원 2008 ETRI Journal Vol.30 No.4
A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.
Ultra-fast Adaptive Frequency-controlled Hysteretic Buck Converter for Portable Devices
Kwang-Ho Kim,Bai-Sun Kong 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5
The paper describes a hysteretic buck converter including a differentiator and an adaptive hysteresis window controller. Differentiating the feedback signal achieves ultra-fast switching of the buck converter. The adaptive hysteresis window control allows a monotonous operation with predictable noise spectrum, and gives way to efficient design for variable supply and output voltages. The measurement results in a 0.13-μm CMOS process indicated that the switching frequency became double times higher, and the voltage ripple was reduced by up to 69%. They also indicated that the normalized switching frequency variation was reduced by 74% with variable VDD and by 63% with variable VOUT. The power efficiency was improved by 3.5% depending on loading condition.
Dual Edge-Triggered NAND-Keeper Flip-Flop for High-Performance VLSI
Kim, Jae-Il,Kong, Bai-Sun The Institute of Electronics and Information Engin 2003 Journal of semiconductor technology and science Vol.3 No.2
This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.
Delay-balanced level converter for dynamic voltage scaling
Min-su Kim,Bai-Sun Kong,Young-Hyun Jun,Sung-Bae Park 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
A novel level converter with balanced rise and fall delays irrespective of supply voltage change is presented. It also provides lower latency than the conventional level converter. The proposed level converter was designed using a 90 ㎚ CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by 93% with up to 16% improvement on speed.
Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links
Hyun-Wook Lim,Bai-Sun Kong,Young-Hyun Jun 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.1
Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ΣΔ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at 10<SUP>-6</SUP> BER increased from 0.261 UI to 0.363 UI with stable loop convergence.