http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
Jang, Cheoljon,Chong, Jongwha,Kim, Jaehwan IET 2014 IET COMPUTERS AND DIGITAL TECHNIQUES Vol.8 No.5
<P>Three-dimensional (3D) integrated circuits, which use a vertically stacked design of 2D planar chips in a 3D arrangement using through-silicon-via (TSV) technology have been developed to minimise chip footprint, enable higher integration density, decrease power consumption and reduce fabrication cost. Floorplanning without considering power can increase the number of power TSVs and bumps needed to solve IR drop constraint in 3D power delivery network. In this study, the authors propose a methodology for minimising the power TSVs and bumps based on power-aware floorplanning using specific power patterns to solve IR drop constraint on the 3D power delivery network. The authors' methodology moves high power-consuming blocks to the dedicated pattern area which is able to minimise the number of power TSVs and bumps while solving the IR drop constraint. The simulation results show that the proposed method can reduce the total number of power TSVs and bumps by 13.7 and 12.2%, respectively, after power-aware floorplanning while solving the IR drop constraint.</P>
Fast Patch-based De-blurring with Directional-oriented Kernel Estimation
Min, Kyeongyuk,Chong, Jongwha Institute of Korean Electrical and Electronics Eng 2017 전기전자학회논문지 Vol.21 No.1
This paper proposes a fast patch-based de-blurring algorithm including kernel estimation based on the angle between the edge and the blur direction. For de-blurring, image patches from the most informative edges in the blurry image are used to estimate a kernel with low computational cost. Moreover, the kernels of each patch are estimated based on the correlation between the edge direction and the blur direction. This makes the final kernel more reliable and creates an accurate latent image from the blurry image. The combination of directionally oriented kernel estimation and patch-based de-blurring is faster and more accurate than existing state-of-the art methods. Experimental results using various test images show that the proposed method achieves its objectives: speed and accuracy.
Subspace-Based Two Way Ranging System Based on CSS Signals
Daegun Oh,Jongwha Chong 대한전자공학회 2010 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
We implemented a subspace-based two way ranging system with chirp spread spectrum (CSS) modem. By using up and down chirp signals of CSS system for range estimation, it is possible to estimate time of arrival of paths accurately by subspace-based estimation. For data communication, synchronization algorithms for CSS signal have been implemented in FPGA and subspace-based time delay estimation algorithm have been implemented in software based on reconfigurable NIOS architecture. We verified the proposed ranging system through experiments using prototype ranging system. Measurements in hallway and room are presented.
Edge-preserving demosaicing method for digital cameras with Bayer-like W-RGB color filter array
( Jongjoo Park ),( Jongwha Chong ) 한국인터넷정보학회 2014 KSII Transactions on Internet and Information Syst Vol.8 No.3
A demosaicing method for a Bayer-like W-RGB color filter array (CFA) is proposed. When reproducing images from a W-RGB CFA, conventional color separation methods for W-RGB CFA are likely to cause blurring near the edges due to rough averaging using a color ratio of neighboring pixels. Moreover, these methods cannot be applied to real-life digital cameras with W-RGB CFA because the methods were proposed under an ideal situation, W=R+G+B, not a real-life situation, W≠R+G+B. To improve edge performance, we propose a method of constant color difference assumption with inversed weight, which uses information from all edge directions for interpolating all missing color channels. The proposed method calculates the correlation between W, R, G, and B to enable its application to real-life digital cameras with W-RGB CFA. Simulations were performed to evaluate the proposed method using images captured from a real-life digital camera with W-RGB CFA. Simulation results shows that we can demosaic by using the proposed algorithm compared with the conventional one in about +34.79% SNR, +11.43% PSNR, +1.54% SSIM and 14.02% S-CIELAB error. Thus, the proposed method demosaics better than the conventional methods.
Fast Patch-based De-blurring with Directional-oriented Kernel Estimation
Kyeongyuk Min,Jongwha Chong 한국전기전자학회 2017 전기전자학회논문지 Vol.21 No.1
This paper proposes a fast patch-based de-blurring algorithm including kernel estimation based on the angle between the edge and the blur direction. For de-blurring, image patches from the most informative edges in the blurry image are used to estimate a kernel with low computational cost. Moreover, the kernels of each patch are estimated based on the correlation between the edge direction and the blur direction. This makes the final kernel more reliable and creates an accurate latent image from the blurry image. The combination of directionally oriented kernel estimation and patch-based de-blurring is faster and more accurate than existing state-of-the art methods. Experimental results using various test images show that the proposed method achieves its objectives: speed and accuracy.
A hybrid coding method for motion-blur reduction in LCD overdrive
Jun Wang,Kyeongyuk Min,Jongwha Chong 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
We propose a novel Adaptive Quantization Coding (AQC) to reduce the error in compression for overdriving technique reducing motion-blur. Considering hardware implementation, we develop a hybrid image coding which uses color converter first, and then uses AQC to compress luminance data as well as Block Truncation Coding (BTC) to compress chrominance data. The simulation results shown that the average PSNR was improved 5.676㏈ comparing with the result of the BTC, and the average SD of error was reduced 50.2% comparing with the result of the BTC. The proposed algorithm is implemented with the verilog HDL and synthesized with the synopsys design compiler using 0.13㎛ Samsung Library.
Jindoo Jeong,Seunghan Baek,Jongwha Chong,Jeoungsig Yoon 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, we propose an algorithm to improve the precision of initial carrier-frequency offset estimation for multiband-OFDM (MB-OFDM) UWB system which is considering the quantization-noise effect. In the general OFDM system, the two adjacent and repeated preamble symbols are used for the initial carrier-frequency synchronization while the performance of the frequencyoffset estimation is bounded by quantization effect generated from analog-to-digital conversion at the receiver. This paper proposes a method in which one-symbol interval between two adjacent preamble symbols for the initial frequency synchronization is extended to multiple-symbol interval between non-adjacent symbols in an extent that phase ambiguity does not occur. In this paper, we also propose an architecture which can optimally implement the proposed multiple-symbol interval estimation method to the MB-OFDM system with 30 preamble symbols on 3-band hopping and with 4-bit A/D conversion at the receiver. Under the channel environments for the MB-OFDM UWB system, the simulation results show that the proposed estimation algorithm can achieve the initial estimation in offset precision less than 5 ppm.
An auto-resize cache structure for high-performance and low-power
Zhirui Liao,Jaehwan Kim,Jongwha Chong 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, we design a cache scheme which can reduce the power consumption and increase the performance of cache through auto-resize of L1 cache, which is called auto-selecting cache scheme. Cache memory occupies a significant fraction of a chip’s overall power consumption. Recent researches advocate using “resizable” to adjust cache capability based on the fact that requirement in applications will reduce cache size and power consumption. Based on the fact that different programs need different sizes of instruction and data cache, an auto-selecting cache scheme is proposed. This scheme can dynamically adjust the sizes of level 1 cache according to program requirement of instruction and data cache. The proposed structure can reduce power consumption and improve cache performance. According to the SPEC2000 simulation, the average power consumption of L1 cache is reduced by 7.43% and the average of energy delay production is improved by 16.08% with auto-selecting cache structure compared traditional one.