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Differential Body-Factor Technique for Characterization of Interface Traps in MOSFETs
Daeyoun Yun,Minkyung Bae,Jaeman Jang,Hagyoul Bae,Ja Sun Shin,Euiyeon Hong,Jieun Lee,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE electron device letters Vol.32 No.9
<P>A differential body-factor technique (DBT) is proposed for characterization of interface traps in MOSFETs employing the differential body factor <I>dm</I>/<I>dV</I><SUB>GS</SUB> instead of the subthreshold slope or the body factor itself. The DBT is independent of the threshold voltage variation and advantageous to apply to MOSFETs with strong nonlinearity in the subthreshold slope caused by a nonuniform distribution of traps over the band gap. We applied the DBT to n- and p-MOSFETs with <I>W</I>/<I>L</I> = 5/0.13, 5/0.18, and 2/0.13μm/μm on the same wafer and obtained identical results. Extracted interface trap density ranges <I>D</I><SUB>it</SUB> = 10<SUP>10</SUP>-10<SUP>11</SUP> cm<SUP>-2</SUP>eV<SUP>-1</SUP> with a U-shaped distribution over the band gap.</P>
Euiyoun Hong,Daeyoun Yun,Hagyoul Bae,Hyunjun Choi,Won Hee Lee,Mihee Uhm,Hyojoon Seo,Jieun Lee,Jaeman Jang,Dae Hwan Kim,Dong Myong Kim IEEE 2012 IEEE electron device letters Vol.33 No.7
<P>A distribution of interface states (<I>D</I><SUB>it</SUB>) in SOI MOSFETs has been characterized by a subbandgap optical differential body-factor (SODBoF) technique. We adopted a subbandgap (<I>E</I><SUB>ph</SUB> <; <I>E</I><SUB>g</SUB>) optical source as a virtual gate on the body-contactless SOI MOSFETs under the subthreshold (<I>V</I><SUB>GS</SUB> <; <I>V</I><SUB>T</SUB>) current-voltage characteristics. Employing a differentiation to the body factor, any possible error from the threshold voltage is also suppressed. We applied the SODBoF technique to n- and p-channel SOI MOSFETs on the same wafer and verified the result. Extracted traps over the bandgap ranges <I>D</I><SUB>it</SUB> = 10<SUP>10</SUP> - 10<SUP>11</SUP> cm<SUP>-2</SUP>·eV<SUP>-1</SUP> with a typical U-shape.</P>
도로 상태 분석을 위한 차량 센서 데이터 수집장치의 구현
최윤희(Yunhee Choi),윤대연(Daeyoun Yun),김창원(Changwon Kim),서정욱(Jungwook Seo),유광호(Kwangho Yoo) 대한전자공학회 2020 대한전자공학회 학술대회 Vol.2020 No.8
Due to the high demand of improved vehicle safety, automotive industry is actively developing active safety systems such as AEB(Autonomous Emergency Braking), AES(Autonomous Emergency Steering). However, in order to optimize such an automatic control system and improve performance, it is very important to consider the influence of the vehicle movement as well as the weather or road surface. Many studies are being conducted to measure and analyze the condition of various road surfaces. In this study we introduce low cost sensor data acquisition system for road condition analysis using raspberry pi computer board. Utilizing this system, synchronized sensor and video data is automatically recorded while driving.
Hagyoul Bae,Jaeman Jang,Ja Sun Shin,Daeyoun Yun,Jieun Lee,Tae Wan Kim,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE electron device letters Vol.32 No.6
<P>A new technique for a separate extraction of the current-path-dependent resistance (R<SUB>SD0</SUB>) from the contact-dependent source and drain resistances (R<SUB>Se</SUB> and R<SUB>De</SUB>) is reported for a single MOSFET. We also report a technique for a separation of V<SUB>GS</SUB>-dependent source and drain resistance (R<SUB>SDi</SUB>) from the V<SUB>GS</SUB>- and L<SUB>eff</SUB>-dependent channel resistance (R<SUB>ch</SUB>) with multiple MOSFETs. We confirm the proposed techniques applied to n-channel MOSFETs with various W/L combinations and obtain R<SUB>Se</SUB> = 10.5 - 12.4 Ω , R<SUB>De</SUB> ≅ 12.7 Ω, and R<SUB>SD0</SUB> = 4.7 Ω for W = 10 μm. V<SUB>GS</SUB>-dependent but L-independent R<SUB>SDi</SUB> is extracted to be 2.8 - 4.2 Ω.</P>
A Novel Double HBT-Based Capacitorless 1T DRAM Cell With Si/SiGe Heterojunctions
Ja Sun Shin,Hagyoul Bae,Jaeman Jang,Daeyoun Yun,Jieun Lee,Euiyoun Hong,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE electron device letters Vol.32 No.7
<P>We propose a novel double heterojunction bipolar transistor (DHBT)-based capacitorless one-transistor (1T) DRAM cell employing a narrow bandgap SiGe body and Si/SiGe heterojunction for a possible next-generation DRAM cell. It has a body with a narrow bandgap and a valence band offset between the source/drain and the body. Through an extended investigation via TCAD simulation, we verified the advantages of the proposed DHBT-based 1T DRAM cell, including an improved excess carrier generation rate, a high current gain, a large sensing margin, and a suppressed sensitivity to the bandgap-narrowing effect in the heavily doped source and drain.</P>
Hagyoul Bae,Inseok Hur,Ja Sun Shin,Daeyoun Yun,Euiyoun Hong,Keum-Dong Jung,Mun-Soo Park,Sunwoong Choi,Won Hee Lee,Mihee Uhm,Dae Hwan Kim,Dong Myong Kim IEEE 2012 IEEE electron device letters Vol.33 No.4
<P>We report a hybrid technique for extraction of structure- and gate-bias-dependent parasitic source/drain (S/D) resistances (<I>RS</I> and <I>RD</I>) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, <I>C</I>- <I>V</I> and <I>I</I> -<I>V</I> measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness <I>T</I><SUB>IGZO</SUB> , the gate length <I>L</I>, and the overlap length <I>L</I><SUB>ov</SUB> between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component <I>RH</I> considering the transfer resistance <I>R</I><SUB>LT</SUB> depending on the transfer length <I>LT</I> and the channel resistance <I>R</I><SUB>CH</SUB>, as well as the vertical components in the S/D <I>R</I><SUB>VS</SUB> and <I>R</I><SUB>VD</SUB>. We confirmed the proposed technique through a separate extraction of <I>VGS</I> -independent contact resistances (<I>R</I><SUB>CS</SUB>, <I>R</I><SUB>CD</SUB>) from the channel length- and <I>VGS</I>-dependent <I>R</I><SUB>LT</SUB> and <I>R</I><SUB>CH</SUB>.</P>
Hagyoul Bae,Sungwoo Jun,Choon Hyeong Jo,Hyunjun Choi,Jaewook Lee,Yun Hyeok Kim,Seonwook Hwang,Hyun Kwang Jeong,Inseok Hur,Woojoon Kim,Daeyoun Yun,Euiyeon Hong,Hyojoon Seo,Dae Hwan Kim,Dong Myong Kim IEEE 2012 IEEE electron device letters Vol.33 No.8
<P>We propose a modified conductance method for extraction of the subgap density of states (DOS) in amorphous indium-gallium-zinc oxide thin-film transistors by using the measured capacitance and conductance through the capacitance-voltage (C-V) measurement. In the proposed method, the subgap DOS [g<SUB>A</SUB>(E)] is extracted from the frequency-dispersive C-V characteristics by localized traps in the active channel region. The extracted g<SUB>A</SUB>(E) shows a superposition of the exponential tail states and the exponential deep states over the bandgap (N<SUB>TA</SUB> = 3 × 10<SUP>18</SUP> cm<SUP>-3</SUP> · eV<SUB>-1</SUB>, N<SUB>DA</SUB> = 2.8 × 10<SUP>17</SUP> cm<SUP>-3</SUP> · eV-1, kT<SUB>TA</SUB> = 0.04 eV, and kT<SUB>DA</SUB> = 0.77 eV). We note that the gate-bias-dependent Cfree by free electron charges can be separated from C<SUB>loc</SUB> by localized trap charges through the proposed method.</P>
Sunyeong Lee,Ja Sun Shin,Jaeman Jang,Hagyoul Bae,Daeyoun Yun,Jieun Lee,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.10 No.5
<P>We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F<SUP>2</SUP> feature size. Thanks to the Si<SUB>0.8</SUB>Ge<SUB>0.2</SUB> superlattice quantum well and silicon dioxide (SiO<SUB>2</SUB>) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10 ms for the retention time.</P>
Hagyoul Bae,Seok Cheon Baek,Sunyeong Lee,Jaeman Jang,Ja Sun Shin,Daeyoun Yun,Hyojong Kim,Dae Hwan Kim,Dong Myong Kim IEEE 2010 IEEE electron device letters Vol.31 No.11
<P>The separate extraction of asymmetric source (<I>R</I><SUB>S</SUB>) and drain (<I>R</I><SUB>D</SUB>) resistances caused by the variations in the layout, process, and device degradation is important in the practical modeling and characterization of MOSFETs and their integrated circuits. We propose a simple “parasitic junction current method” (PJCM) for the separate extraction of <I>R</I><SUB>S</SUB>, <I>R</I><SUB>D</SUB>, and <I>R</I><SUB>SUB</SUB> (substrate resistance) in MOSFETs. We applied the proposed PJCM to n-channel MOSFETs with different <I>W</I>/<I>L</I> combinations and verified its usefulness in the robust extraction of <I>R</I><SUB>S</SUB>, <I>R</I><SUB>D</SUB>, and <I>R</I><SUB>SUB</SUB>.</P>