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전희석,윤여남,송익현,신형철,Jhon, Hee-Sauk,Yoon, Yeo-Nam,Song, Ick-Hyun,Shin, Hyung-Cheol The Institute of Electronics and Information Engin 2007 電子工學會論文誌-CI (Computer and Information) Vol.44 No.10
본 논문에서는 vertical shunt symmetric inductor를 이용하여 CMOS LNA의 설계에 있어서 회로의 면적을 줄이는 설계기술 및 구현에 관한 내용을 제시하고자 한다. 본 연구에 있어서 vertical shunt symmetric inductor는 LNA의 입력단과 출력단을 3GHz로 정합하기 위해서 사용되었다. 이렇게 구현된 보다 면적에 있어서 효율적인 증폭기를 0.18um digital logic공정으로 구현되었다. 본 논문에서는 일반적으로 LNA에서 사용하고 있는 inductor를 이용하는 경우와, vertical shunt symmetric inductor를 이용하여 LNA를 설계하는 경우에 대한 부분을 비교하였고, 최종적으로 면적에 효율적인 회로설계 기술을 제시하고자 한다. This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using vertical shunt symmetric inductor. We applied a vertical shunt symmetric inductor to match the input and output in 3 GHz CMOS LNA to reduce the circuit area. This size efficient amplifier has been designed in a $0.18\;{\mu}m$ digital logic CMOS process. In this paper, the case of conventional asymmetric inductor, and vertical shunt symmetrical inductor with a relatively higher number of turns have been compared in order to efficient a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.
Low Cost CMOS LNA Design Using On-Chip Size Efficient Inductors
전희석(Hee-Sauk Jhon),송익현(Ickhyun Song),윤여남(Yeonam Yun),구민석(Minsuk Koo),정학철(Hakchul Jung),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using size efficient inductors. We applied vertical shunt symmetric and helical inductor to match the input and output in 2.4 ㎓ CMOS LNA to reduce the circuit area. In this paper, the case of conventional LNA using asymmetric inductor, and that of ones using vertical shunt symmetrical and helical inductor with a relatively higher number of turns have been compared in order to present a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.
Noise Interpolation of MOSFET in Moderate Inversion and Its Verification in Low Noise Amplifier
송익현(Ickhyun Song),구민석(Min Suk Koo),정학철(Hakchul Jung),이상훈(Sanghoon Lee),Shen Yehao,전희석(Hee Sauk Jhon),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
MOSFET noise in moderate inversion region is interpolated using two noise models in the regions of subthreshold and strong inversion. With these channel noise value, a CMOS low noise amplifier (LNA) operating in moderate inversion region is designed for verification and its noise characteristic is presented.