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고객의 지연보고를 고려한 보증수리내역자료에서의 고장률 추정
박종훈(J. H. Park),김영훈(Y. H. Kim),백장현(J. H. Baek),이창훈(C. H. Lie) 대한산업공학회 2010 산업공학 Vol.23 No.2
Warranty claim data analysis is a useful tool for the manufacturer because it contains many useful informations regarding reliability of the product in the real-world environments. Because of the nature of uncertainty and the incompleteness of data, some bias patterns are observed on warranty claim rate known as ‘spikes’. Two types of spikes are considered. One is due to manufacturing-related failures. The other is caused by customer’s behavior. This paper proposes a model by considering two types of spikes. Warranty claim data is analyzed with the proposed model. To represent spikes observed on the early warranty period, we classify failures into manufacturing-related failures and usage-related failures. Uniform distribution is assumed for the time delayed to diagnose and report by customers. By reducing maximum value of the delayed time by customers, the proposed model characterizes customer’s rush in the vicinity of the warranty expiration limit. Experimental results by using the real warranty claim data show that the proposed model is better than the existing one in respect to MSE(Mean Squared Error). Moreover it is expected to estimate the failure rate more realistically with proposed model because it considers the delayed time to diagnose and report by customers.
초대형 집적회로 설계 방법론 개발 : 시모스 셀 데이터 베이스 구성 Data Base Construction of CMOS Cell
이문기,박춘성,박종훈 연세대학교 산업기술연구소 1985 논문집 Vol.17 No.2
본 논문은 이중 금속 Poly Gate Process와 3㎛ Design Rule을 이용한 CMOS Standard Cell Library의 설계에 관한 것이다. 설계된 Library는 Random Logic Gate, Flip-Flop 그리고 입·출력 소자등 모두 33개로 이루어졌다. Cell의 높이는 모두 98㎛로 일정하고 1Grid는 9㎛이다. 그리고 모든 Cell에 대해서 부하에 따른 Delay Time을 구하여 System 설계시 자료로써 이용하기 용이하게 하였다. Random Logic의 대표적인 Cell인 AO2(2 ANDS INTO 2NOR)의 경우 1 Fanout 에 대한 Delay Time ??, ?? 은 각각 2.99(㎱), 1.87(㎱)이다. This paper describes the CMOS standard cell library implemented in double metal poly gate process and 3㎛ design rule. This standard cell library total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98㎛, and width in multiple constant grid of 9㎛. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. The delay time ?? and ?? for typical random logic cell, A02(2ANDS INTO 2NOR), are respectively 2.99 and 1.87 (㎱) for 1 fanout. This cell can be used to achieve high speed digital system, design as well as a reduction in chip area compared to gate array.