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남재원,조영균,Nam, Jae-Won,Cho, Young-Kyun 중소기업융합학회 2021 융합정보논문지 Vol.11 No.9
본 연구는 시간-보간법을 적용한 FLASH analog-to-digital converter (ADC)에 관한 것이다. 시간-보간법은 기존의 FLASH ADC에서 요구되는 전압영역 비교기의 개수를 줄일 수 있으며 이 따른 전력 소모 및 칩 면적의 절약을 기대할 수 있다. 본 연구에서는 5-bit, 즉 31개의 양자화 레벨을 갖는 ADC를 설계 및 구현하였으며, 16개의 양자화 레벨은 기존의 전압영역 비교기 방식을 유지하고, 나머지 15개의 양자화 레벨은 시간영역 비교기를 통하여 처리되도록 구성하여, 기존 5-bit FLASH ADC 대비 전압영역 비교기의 숫자를 48.4% 줄일 수 있었다. 시제품은 14 nm Fin Field-effect transistor (FinFET) 공정으로 제작되었으며 구현면적은 0.0024 mm<sup>2</sup>, 전력소모는 0.8 V 전원전압에서 0.82 mW로 측정되었으며, 400 MS/s의 변환속도 21 MHz 정현파 입력에 대하여 ADC는 28.03 dB의 신호-대-잡음비 (SNDR), 즉 4.36 유효비트(ENOB)의 성능을 보였다. A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.
현진원(Jin-Won Hyun),김재윤(Jae-Yoon Kim),김승재(Seung-Jae Kim),남재원(Jae-Won Nam) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
Rapid technology scale-down results in significant performance improvement on digital processing speed associated with enhanced power efficiency due to reduced supply voltage. However, relative circuit noise power becomes enlarged. Thus, low noise clock generation circuits are highly required. As a key factor of evaluating the clocking system, analyzing jitter contribution becomes essential. However, the more technology scaling down has been progressed, the more jitter analysis has been complicated. In this paper, we implemented 4 methods to enhance jitter performance of delay-locked-loop (DLL) circuit to support systematic jitter analysis. After applying our proposed DLL design optimization technique targeting for 1GHz clock generation under 1.2V supply voltage, we obtained 63.7% jitter noise reduction in 65nm standard CMOS technology.
최유림(You-Lim Choi),임성현(Seung-Hyeon Im),정한수(Han-Soo Jung),김승모(Seung-Mo Kim),남재원(Jae-Won Nam) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
Electric vehicles (EVs) are considered a great alternative for reducing carbon emissions, and South Korea is striving to increase the penetration rate of EVs through supportive policies. However, the number of EV chargers is insufficient compared to the increasing penetration rate of EVs. Given the high cost and the requirement for high voltage, selecting an accurate installation location is crucial. Therefore, we propose a machine learning-based approach to predict the appropriate location for EV chargers using data that influences the selection of charger locations on Jeju Island. Additionally, we present a method for adjusting various machine learning conditions to enable precise selection of EV charger locations with high prediction accuracy.