Low-Power Convolutional Neural Network Processor for a Face-Recognition System

Bong, Kyeongryeol,Choi, Sungpill,Kim, Changhyeon,Yoo, Hoi-Jun IEEE 2017 IEEE micro Vol.37 No.6

<P>The authors propose a low-power convolutional neural network (CNN)-based face recognition system for user authentication in smart devices. The system comprises an always-on functional CMOS image sensor (CIS) for imaging and face detection, and a low-power CNN processor (CNNP) for face verification. Implemented in 65-nm CMOS technology, the system consumes 0.62 mW to evaluate one face at 1 fps and achieves 97 percent accuracy.</P>

A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform

Kim, Changhyeon,Bong, Kyeongryeol,Choi, Sungpill,Lee, Kyuho Jason,Yoo, Hoi-Jun IEEE 2016 IEEE transactions on circuits and systems. a publi Vol.63 No.12

<P>A low-latency and low-power stereo matching accelerator is monolithically integrated with a CMOS image sensor (CIS) for mobile applications. To reduce the overall latency, focal-plane processing is adopted by using the proposed analog census transform circuit (ACTC), and the image readout is pipelined with the following stereo matching process. In addition, a novel focal-plane rectification pixel array (FRPA) merges the rectification with the image readout without any additional processing latency. For area-efficient pixel design, sparse rectification is proposed, and the image rectification is implemented with only two additional switches in each pixel. A stereo matching digital processor (SMDP) is integrated with the CIS for cost aggregation. We present the full design including the layout with a 65 nm CMOS process, and the FRPA, the ACTC, and the SMDP achieve 11.0 ms latency with complete stereo matching stages, which is suitable for a smooth user interface. As a result, the 2-chip stereo matching system dissipates 573.9 mu J/frame and achieves 17% energy reduction compared to a previous stereo matching SoC.</P>

A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses

Injoon Hong,Kyeongryeol Bong,Dongjoo Shin,Seongwook Park,Kyuho Jason Lee,Youchang Kim,Hoi-Jun Yoo IEEE 2016 IEEE journal of solid-state circuits Vol.51 No.1

<P>A low-power object recognition (OR) system with intuitive gaze user interface (UI) is proposed for battery-powered smart glasses. For low-power gaze UI, we propose a low-power single-chip gaze estimation sensor, called gaze image sensor (GIS). In GIS, a novel column-parallel pupil edge detection circuit (PEDC) with new pupil edge detection algorithm XY pupil detection (XY-PD) is proposed which results in 2.9x power reduction with 16x larger resolution compared to previous work. Also, a logarithmic SIMD processor is proposed for robust pupil center estimation, <1 pixel error, with low-power floating-point implementation. For OR, low-power multicore OR processor (ORP) is implemented. In ORP, task-level pipeline with keypoint-level scoring is proposed to reduce the number of cores as well as the operating frequency of keypoint-matching processor (KMP) for low-power consumption. Also, dual-mode convolutional neural network processor (CNNP) is designed for fast tile selection without external memory accesses. In addition, a pipelined descriptor generation processor (DGP) with LUT-based nonlinear operation is newly proposed for low-power OR. Lastly, dynamic voltage and frequency scaling (DVFS) for dynamic power reduction in ORP is applied. Combining both of the GIS and ORP fabricated in 65 nm CMOS logic process, only 75 mW average power consumption is achieved with real-time OR performance, which is 1.2x and 4.4x lower power than the previously published work.</P>

A 502-GOPS and 0.984-mW Dual-Mode Intelligent ADAS SoC With Real-Time Semiglobal Matching and Intention Prediction for Smart Automotive Black Box System

Lee, Kyuho Jason,Bong, Kyeongryeol,Kim, Changhyeon,Jang, Jaeeun,Lee, Kyoung-Rog,Lee, Jihee,Kim, Gyeonghoon,Yoo, Hoi-Jun IEEE 2017 IEEE journal of solid-state circuits Vol.52 No.1

<P>The advanced driver assistance system (ADAS) for adaptive cruise control and collision avoidance is strongly dependent upon the robust image recognition technology such as lane detection, vehicle/pedestrian detection, and traffic sign recognition. However, the conventional ADAS cannot realize more advanced collision evasion in real environments due to the absence of intelligent vehicle/pedestrian behavior analysis. Moreover, accurate distance estimation is essential in ADAS applications and semiglobal matching (SGM) is most widely adopted for high accuracy, but its system-on-chip (SoC) implementation is difficult due to the massive external memory bandwidth. In this paper, an ADAS SoC with behavior analysis with Artificial Intelligence functions and hardware implementation of SGM is proposed. The proposed SoC has dual-mode operations of highperformance operation for intelligent ADAS with real-time SGM in D-Mode (d-mode) and ultralow-power operation for black box system in parking-mode. It features: 1) task-level pipelined SGM processor to reduce external memory bandwidth by 85.8%; 2) region-of-interest generation processor to reduce 86.2% of computation; 3) mixed-mode intention prediction engine for dualmode intelligence; and 4) dynamic voltage and frequency scaling control to save 36.2% of power in d-mode. The proposed ADAS processor achieves 862 GOPS/W energy efficiency and 31.4GOPS/ mm(2) area efficiency, which are 1.53x and 1.75x improvements than the state of the art, with 30 frames/s throughput under 720p stereo inputs.</P>

An 87-<tex> $\hbox{mA}\cdot \min$</tex> Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System

Kiseok Song,Unsoo Ha,Jaehyuk Lee,Kyeongryeol Bong,Hoi-Jun Yoo IEEE 2014 IEEE journal of solid-state circuits Vol.49 No.1

<P>A bio-feedback iontophoresis controller IC is implemented into a fabric patch for transdermal drug delivery. An iontophoresis stimulator front-end (ISFE) can provide programmable stimulation current in the range of 16-512-μA amplitude, DC-500-Hz frequency, and 3% -100% duty cycle for controllable drug delivery. For safe and robust electrical stimulation, a failure detection circuit monitors the stimulation current to prevent overcurrent and stimulation voltage saturation. For bio-feedback operation, a dual-mode impedance sensor (DMIS) measures load and tissue impedances in the range of 5-50 kΩ and 5 Ω-1 kΩ, respectively. In the DMIS, the gain of a programmable gain amplifier and the injected current level of a chopper-modulated current source are automatically controlled to minimize power consumption. The proposed IC occupies 2.35 mm × 2.35 mm including pads in a 0.11-μm 1P6M CMOS technology and dissipates a peak power of 2.2 mW. The proposed IC is directly integrated on a 9 cm × 4 cm fabric circuit board together with a 6.2-mAh coin battery for convenient iontophoresis treatment. The proposed system provides a maximum dosage range of 87 mA·min, which is larger range than the 80- mA·min dosage range of a commercial iontophoresis patch. Using a reconfigurable tetra-polar electrode configuration, load and tissue impedances are measured during the iontophoresis treatment to provide bio-feedback. The proposed iontophoresis system is successfully verified by both in-vitro and in-vivo tests.</P>

An Augmented Reality Processor with a Congestion-Aware Network-on-Chip Scheduler

Gyeonghoon Kim,Donghyun Kim,Seongwook Park,Youchang Kim,Kyuho Lee,Injoon Hong,Kyeongryeol Bong,Hoi-Jun Yoo IEEE 2014 IEEE micro Vol.34 No.6

<P>For a markerless augmented reality system that can operate all day, the authors implemented a low-power Basic On-Chip Network-Augmented Reality (BONE-AR) processor to execute object recognition, camera pose estimation, and 3D graphics rendering in real time for an HD resolution video input. BONE-AR employs six clusters of heterogeneous SIMD processors distributed on the mesh topology network on a chip (NoC) to exploit data- and task-level parallelism. A visual attention algorithm reduces overall workload by removing background clutters from the input video frames, but also incurs NoC congestion because of a dynamically fluctuating workload. The authors propose a congestion-aware scheduler that detects and resolves the NoC congestion to prevent throughput degradation of a task-level pipeline.</P>

A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications

Gyeonghoon Kim,Kyuho Lee,Youchang Kim,Seongwook Park,Injoon Hong,Kyeongryeol Bong,Hoi-Jun Yoo IEEE 2015 IEEE journal of solid-state circuits Vol.50 No.1

<P>Real-time augmented reality (AR) is actively studied for the future user interface and experience in high-performance head-mounted display (HMD) systems. The small battery size and limited computing power of the current HMD, however, fail to implement the real-time markerless AR in the HMD. In this paper, we propose a real-time and low-power AR processor for advanced 3D-AR HMD applications. For the high throughput, the processor adopts task-level pipelined SIMD-PE clusters and a congestion-aware network-on-chip (NoC). Both of these two features exploit the high data-level parallelism (DLP) and task-level parallelism (TLP) with the pipelined multicore architecture. For the low power consumption, it employs a vocabulary forest accelerator and a mixed-mode support vector machine (SVM)-based DVFS control to reduce unnecessary external memory accesses and core activation. The proposed 4 mm × 8 mm HMD AR processor is fabricated using 65 nm CMOS technology for a battery-powered HMD platform with real-time AR operation. It consumes 381 mW average power and 778 mW peak power at 250 MHz operating frequency and 1.2 V supply voltage. It achieves 1.22 TOPS peak performance and 1.57 TOPS/W energy efficiency, which are, respectively, 3.58 × and 1.18 × higher than the state of the art.</P>