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Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique
Daichi Omoto,Keiji Kishine,Hiromi Inaba,Tomoki Tanaka 대한전자공학회 2016 IEIE Transactions on Smart Processing & Computing Vol.5 No.3
This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the data frame configuration. To add a routing control signal, called the “labeling signal” in this paper, to the data frame, we use a frequency modulation technique on the transmitted frame. This means you need not change the data frame when you transmit additional signals. Using a prototype system comprising a field-programmable gate array and discrete elements, we investigate the system performance and devise a method to achieve high resolution. A three-channel routing control for a 10 Gb/s data frame was achieved, which confirms the advantages of the proposed system.
A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-㎚ CMOS
Tomoki Tanaka,Keiji Kishine,Akira Tsuchiya,Hiromi Inaba,Daichi Omoto 대한전자공학회 2016 IEIE Transactions on Smart Processing & Computing Vol.5 No.3
Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-㎚ CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.
Ito, Takuma,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ishikura, Keisuke Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.4
If it were possible to control four sets of PMSMs in place of induction motors by using one inverter, we could attain efficient driving trains. In this paper, a method for controlling three sets of PMSMs with one inverter is shown. Additionally, this shows the method to control four sets of PMSMs with one inverter and the results of a simulation with the proposed method.
Ishikura, Keisuke,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ito, Takuma Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.4
Parallel operation systems have an advantage in that they can be constructed quickly and inexpensively by combining existing electric power converters. However, in this case, there is a peculiar problem in that a cross current flows between the electric power converters. To design a control system more simply and commonalize the core of combination reactors, we reviewed a system construction method for parallel operation systems constructed with three electric power converters.
Method Controlling Two or More Sets of PMSM by One Inverter on a Railway Vehicle
Ito, Takuma,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ishikura, Keisuke Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.2
If two or more Permanent Magnet Synchronous Motors (PMSM) can be controlled by one inverter, a train can be driven by less energy than the present Induction Motor (IM) drive system. First, this paper proposes a method for simulating the movement of wheels and a vehicle to develop a control method. Next, a method is presented for controlling two or more PMSMs by one inverter.
Parallel Multiple Electric Power Conversion System Constructed by Connecting Three Power Converters
Nakai, Mitsuki,Inaba, Hiromi,Kishine, Keiji,Ishikura, Keisuke Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.3
The electric power conversion system constructed by connecting two or more power converters in parallel is an advantageous method for making to large capacity and standardization. In this paper, the control method of cross current when three power converters are operated is examined, and it reexamined a preferable system construction method.
Ishikura, Keisuke,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ito, Takuma Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.3
A large capacity power conversion system constructed by using two or more existing power converters has a lot of flexibility in how the power converters are used. However, at the same time, it has a problem of cross current flows between power converters. The cross current must be suppressed by controlling the system while miniaturizing the combination reactor. This paper focuses on two current control methods of a power conversion system constructed by using two power converters connected in parallel supplying the same power. In order to elucidate the control performance of cross current, each control method which are aimed at controlling cross current and not directly controlling it are examined in simulations.
Design Method for Active-shunt-feedback Type Inductorless Low-noise Amplifiers in 65-nm CMOS
Toshiyuki Inoue,Akira Tsuchiya,Keiji Kishine 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.2
We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, bandwidth, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.
A Method for Accelerating the Inference Process of FPGA-based LSTM for Biometric Systems
Ukyo Yoshimura,Toshiyuki Inoue,Akira Tsuchiya,Keiji Kishine 대한전자공학회 2021 IEIE Transactions on Smart Processing & Computing Vol.10 No.5
Biometric systems require the regression and classification of biological sensing data, which are both carried out using machine learning. Long short-term memory (LSTM) is one of the most common methods used for regression and classification. We have developed and implemented a low-energy LSTM algorithm for the regression of microwave sensor signals in a small-scale FPGA. Experimental results show that the FPGA-based parallel-pipelined unrolled algorithm can reduce the computation time by 95% compared to an FPGA-based sequential algorithm. In addition, we found that the power consumption can be reduced by 92% and 91% compared to that obtained with a high-end GPU and CPU, respectively.
10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS
Hiromu Uemura,Kosuke Furuichi,Natsuyuki Koda,Hiromi Inaba,Keiji Kishine 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.2
Currently, there is a great demand for high speed and large capacity communication systems. Therefore, it is important to develop circuit and device technologies that support these systems. Furthermore, it is important that high speed and large capacity systems are developed based on those technologies. In this paper, we propose a transmitter design method for the transmission system that the additional signal add to 10-Gb/s signal. The system transmits the data frames and the additional information simultaneously. To add the additional information, called the "labeling signal", to the data frames, we perform a frequency modulation technique on the transmitted data frames. To confirm the performance of the proposed circuit and design method, we fabricate an IC with the proposed system’s transmitter by using the 65-nm CMOS process. We confirm that the data frames are frequency modulated and the transmitter generates the frequency-modulated data frames.