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Secure Integrated Circuit with Physical Attack Detection based on Reconfigurable Top Metal Shield
Yeongjin Mun,Hyungseup Kim,Byeoncheol Lee,Kwonsang Han,Jae-SungKim,Ji-Hoon Kim,Byong-Deok Choi,Dong Kyue Kim,Hyoungho Ko 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.3
Invasive physical attacks on integrated circuits (ICs), such as de-packaging, focused ion beam (FIB) chip editing, and micro-probing attempts, constitute security threats for chips with potentially valuable information, such as smart cards. Using a state-of-the-art circuit-editing technique, an attacker can remove an IC’s top metal layer, leaving its secure information exposed to micro-probing attacks. Security ICs can be seriously threatened by such attacks and thus require on-chip countermeasures. Conventional active shields, however, have difficulty coping with physical attacks based on FIB chip editing (i.e., bypassing the top metal shield). This study presents a novel countermeasure against physical attacks based on the use of a reconfigurable metal shield for both top metal removal and micro-probing attack detection. This shield consists of two circuits: an FIB chip editing detection circuit consisting of a random number generator and a micro-probing attempt detection circuit consisting of two conditionally synchronized ring oscillators. Both circuits share a randomly reconfigured top metal shield, which represents a promising solution for security against state-of-the-art invasive attacks.
Low-Power and Low-Noise Capacitive Sensing IC Using Opamp Sharing Technique
Park, Yunjong,Kim, Hyungseup,Mun, Yeongjin,Ko, Youngwoon,Cho, Dong-Il Dan,Ko, Hyoungho IEEE 2016 IEEE SENSORS JOURNAL Vol.16 No.22
<P>This letter presents a low-power and low-noise capacitive sensing IC using opamp sharing technique. The proposed IC reduces both the power consumption and the required circuit area using the opamp sharing technique while maintaining low noise characteristics. A correlated double sampling technique is adopted to reduce the low-frequency noise, including the 1/f noise. An automatic offset calibration loop can automatically reduce the offset parasitic capacitance in the range from -10.8 to +10.8 pF. The power consumption and the active circuit area are 1.02 mW and 2.12 mm(2), respectively. The integrated input referred capacitance noise is 0.164 aF(RMS) with a bandwidth of 400 Hz.</P>