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Improved determination ofBKwith staggered quarks
Bae, Taegil,Jang, Yong-Chull,Jeong, Hwancheol,Jung, Chulwoo,Kim, Hyung-Jin,Kim, Jangho,Kim, Jongjeong,Kim, Kwangwoo,Kim, Sunghee,Lee, Weonjong,Leem, Jaehoon,Pak, Jeonghwan,Park, Sungwoo,Sharpe, Stephe American Physical Society 2014 PHYSICAL REVIEW D - Vol.89 No.7
A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation
Bae, Sang-Geun,Kim, Gyungmin,Kim, Chulwoo IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.10
<P>This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio (d) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a -104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm(2) area in a 65-nm CMOS process.</P>
Bae, Sang-Geun,Kim, Yongtae,Park, Yunsoo,Kim, Chulwoo Institute of Electrical and Electronics Engineers 2017 IEEE journal of solid-state circuits Vol. No.
<P>True random number generators (TRNGs) are important in data encryption for information security applications. In this paper, we propose a TRNG that utilizes a comparator in the common-mode operation and the sampling uncertainty of a D flip-flop (DFF). The comparator output is affected by the input common-mode noise and the noise that is simultaneously self-induced. A slicer generates an unpredictable and asynchronous pulse to the input of the DFF according to the output-referred noise of the comparator. By sampling the random pulse with a 3-GHz external clock, there is a sampling uncertainty, which helps to increase the random quality. As a result, we use the independent two random sources for TRNG. The area of the designed circuit is 1609 mu m(2). In spite of the small size, the data rate of the proposed TRNG is 3 Gb/s. We verify that the output bit stream passes all of the National Institute of Standards and Technology test suites. We fabricate the TRNG in a 65-nm CMOS process with a 1.2-V supply voltage. The power consumption of the proposed TRNG is 5 mW, and the energy per bit is 1.6 pJ/b.</P>
Bae, Sang-Geun,Hwang, Sewook,Song, Junyoung,Lee, Yeonho,Kim, Chulwoo IEEE 2019 IEEE transactions on circuits and systems. a publi Vol.66 No.2
<P>A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a <TEX>${\Delta } {\Sigma }$</TEX> modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ( <TEX>$ {f}_{{\text {LBW}}}$</TEX>). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of <TEX>$ {f}_{\text {LBW}}$</TEX> variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest <TEX>$ {f}_{\text {LBW}}$</TEX>. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm<SUP>2</SUP>.</P>
Jun, Jaehun,Bae, Sang-Geun,Lee, Yeonho,Kim, Chulwoo IEEE 2018 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.65 No.11
<P>A spread-spectrum clock generator is implemented using a nested modulation profile to reduce the peak power levels of radiated electro-magnetic emissions in display products. The display data interface is a potential source of interference, and the spread spectrum technique has been extensively used for display interfaces. The proposed nested profile can further reduce electro-magnetic interference without any degradation in the other characteristics. A test chip was fabricated using a 55-nm CMOS process, and the test results indicate a 41-dB reduction. The sensitivity of a wireless receiver to interference is tested, and the EVM results for the proposed nested profile exhibits an improvement of 1.4 dB compared to those of the triangular profile.</P>
Slurry Temperature Effect on Copper CMP
Pengzhan Liu,SungHoon Bae,Seokjun Hong,Chulwoo Bae,Taesung Kim 대한기계학회 2021 대한기계학회 춘추학술대회 Vol.2021 No.5
During the process of chemical mechanical polishing, much heat was generated due to friction force between CMP pad and wafer. Wafer and pad surface temperature had a stepped upward trend with the beginning of polishing process. The effects on chemical reaction and mechanical mechanism were investigated separately. BTA was proved to be ineffective in high temperature slurry environment. Other chemical reaction such as corrosion and oxidation also accelerated. But temperature did not influence the slurry particle size. By using high temperature slurry, the polishing temperature conditions at the later stage could be achieved directly, and removal rate also increased correspondingly.
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
Sewook Hwang,Junyoung Song,Sang-Geun Bae,Yeonho Lee,Chulwoo Kim IEEE 2016 IEEE transactions on very large scale integration Vol.24 No.3
<P>An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with <10(-12) BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10(-12) BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm(2) in a 0.13-mu m CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.</P>