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SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA
Bishwajeet Pandey,Vandana Thind,Simran Kaur Sandhu,Tamanna Walia,Sumit Sharma 보안공학연구지원센터 2015 International Journal of Security and Its Applicat Vol.9 No.7
In this particular work, we have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA. We have used Xilinx ISE software development kit for all the observation done in this particular research work. Here, we have taken SSTL (Stub-Series Terminated Logic) as input-output standard. We have considered six sub-categories of SSTL (i.e. SSTL135, SSTL135_R, SSTL15, SSTL15_R, SSTL18_I and SSTL18_II) for four different WLAN frequencies (i.e. 2.4GHz, 3.6GHz, 4.9GHz, and 5.9GHz). We have done analysis considering five basic powers i.e. clock power, logic power, signal power, IOs power, leakage power and total power. There is 50-60% reduction in power dissipation, which is possible with proper selection of the most energy efficient IO standards i.e. SSTL135_R among SSTL logic families.
A Study of Today’s A.I. through Chatbots and Rediscovery of Machine Intelligence
Anirudh Khanna,Bishwajeet Pandey,Kushagra Vashishta,Kartik Kalia,Bhale Pradeepkumar,Teerath Das 보안공학연구지원센터 2015 International Journal of u- and e- Service, Scienc Vol.8 No.7
Artificial Intelligence in machines is a very challenging discussion. It involves the creation of machines which can simulate intelligence. This paper discusses some of the current trends and practices in AI and subsequently offers alternative theory for improvement in some of today’s prominent and widely accepted postulates. For this, focus on the structuring and functioning of a simple A.I. system - chatbots (or chatter bots) is made. The paper shows how current approach towards A.I. is not adequate and offers a new theory that discusses machine intelligence, throwing light to the future of intelligent systems.
FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology
Vandana Thind,Bishwajeet Pandey,Kartik Kalia,D M Akbar Hussain,Teerath Das,Tanesh Kumar 보안공학연구지원센터 2016 International Journal of Software Engineering and Vol.10 No.6
In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.
Aditi Moudgil,Kanika Garg,Bishwajeet Pandey 보안공학연구지원센터 2015 International Journal of Smart Home Vol.9 No.9
In this work, we are making Energy Efficient Internet of Things (IoTs) Enable RAM. In order to make it energy efficient, we are using low voltage complementary metal oxide semiconductor (LVCMOS) Standards. We are using the 3 different members of LVCMOS IO standards family at different FGPA (virtex-5 and virtex-6) and searching the most energy efficient among them. We are inserting 128-bit IP address in RAM to make internet of things enable RAM. Finally, we are operating our IOTs Enable RAM with different operating frequency of I3, I5, I7, Moto-E and Moto-X.
Thermal aware Internet of Things Enable Energy Efficient Encoder Design for Security on FPGA
Deepa Singh,Kanika Garg,Ravneet Singh,Bishwajeet Pandey,Kartik Kalia,Hasmatullah Noori 보안공학연구지원센터 2015 International Journal of Security and Its Applicat Vol.9 No.6
In this work, we are going to use thermal aware approach in Encoder design and also testing thermal stability by working on different ambient temperatures 298.15K, 308.15K, 318.15K, 328,15K, 338.15K and 348.15K and 358.15K. We have observe the compatibility of our device with wireless network by working on different I/O standards (LVCMOS15 and LVCMOS25) . There is 30.29% reduction in leakage power, when we scale down temperature from 358.15K to 298.15K using LVCMOS15 as I/O standard on 40nm Virtex FPGA. Leakage power is calculated for 65nm FPGA and 90nm FPGA as well .In this work, we are using Verilog Hardware Description Language.
Mumtaz Hussain Soomro,Sayed Hyder Abbas Musavi,Bishwajeet Pandey 보안공학연구지원센터 2016 International Journal of Bio-Science and Bio-Techn Vol.8 No.4
In this research, a novel method based on Canonical Correlation Analysis (CCA) and Artificial Neural Network (ANN) to detect epileptic seizures from EEG signals is proposed. CCA was applied on EEG signals and feature vectors corresponding to Eigen values were extracted. These Eigen values were fed as input to Artificial Neural Network (ANN)’s widely explored model Multilayer Perceptron Neural Networks (MLPNNs) for classification between occurrence of non-epileptic seizures and epileptic seizures. The extracted Eigen values using CCA proved to be a better epileptic seizures detector and provide average classification accuracy, sensitivity and specificity as 92.583%, 93.25% and 91% respectively.