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RISS 인기검색어
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- 저자 : Arka Dutta (검색결과 2 건)
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Comparisons between Dual and Tri Material Gate on a 32 nm Double Gate MOSFET
Arpan Dasgupta,Rahul Das,Shramana Chakraborty,Arka Dutta,Atanu Kundu,Chandan K. Sarkar 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2016 NANO Vol.11 No.10
The paper reports a comparative analysis between the dual material gate double gate (DMG-DG) nMOSFET and the tri material gate double gate (TMG-DG) nMOSFET in terms of their analog and RF performance. Three different devices having the DMG-DG structure have been considered. Each of the devices have different higher workfunction material gate length (L1) to lower workfunction material gate length (L2) ratio (L1:L2). Along with the three devices, the performance of the TMG-DG nMOSFET is compared. The analog parameters considered for the comparison are the drain current (Ids), the transconductance (gm), the transconductance generation factor (gm/Ids) and the intrinsic gain (gmRo). The drain induced barrier lowering (DIBL) of the devices is compared. The RF analysis is performed using the non quasi static (NQS) approach. We consider the intrinsic gate to source capacitances (Cgs), the intrinsic gate to drain capacitance (Cgd), the intrinsic gate to source resistances (Rgs), the intrinsic gate to drain resistance (Rgd), the transport delay (τm), the unity current gain cut-off frequency (fT ) and the max frequency of oscillation (fmax) for the RF comparisons. A single stage amplifier is also implemented using the devices for a circuit comparison.
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Sarosij Adak,Sanjit Kumar Swain,Arka Dutta 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2016 NANO Vol.11 No.9
Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), Ion/Ioff, Vth roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using driftdiffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.
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