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3.2Gb/s Forwarded Clocking 시스템을 위한 CLK Lane Transceiver 설계
한찬흠(Chan-Heum Han),채주형(Joo-Hyung Chae) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
In this paper, we present the implementation CLK lane transceiver for 3.2Gb/s forwarded clocking system. The transceiver is designed for halfduplex bi-directional communication and is compatible with half-rate structure for data lane transmitter and quarter-rate structure for receiver. In addition, termination scheme for the half-duplex system, circuit structure, and post-layout simulation results are presented.
쿼터-레이트를 사용한 메모리 인터페이스용 단일 종단 NRZ 수신기 설계
이기수(Ki-Soo Lee),채주형(Joo-Hyung Chae) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
In this paper, A single-ended NRZ receiver for memory interface using quarter-rate is presented, and overall structure, operation principle, and necessity are described. The proposed circuit was designed using a 28nm CMOS process. A verification was performed at the data rate of 1.6Gb/s and 3.2Gb/s, and under various process corners.
단일 종단 NRZ 전압 모드 드라이버의 Impedance Matching을 위한 ZQ Code 분석 및 효과
이종찬(Jong-Chan Lee),채주형(Joo-Hyung Chae) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
To ensure the reliability of signal transmission necessary for exchanging data in memory interfaces, impedance matching is required. As the data transmission speed increases, signal noise increases, making impedance matching a critical element for system optimization. In addition, errors in impedance matching can occur due to PVT (Power, Voltage, Temperature) variations, and these errors can directly affect system operation. Therefore, impedance matching for improving signal integrity under PVT variations is essential in memory interfaces. This paper discusses single-ended voltagemode NRZ drivers for memory interfaces and analyzes the effect of ZQ codes for impedance matching.
차세대 메모리 인터페이스를 위한 2-tap Feed-forward Equalizer를 적용한 30-Gb/s PAM- 3 송신기 설계
최병두(Byung-Du Choi),채주형(Joo-Hyung Chae) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
This paper addresses the demand for highbandwidth memory systems and multi-level signaling is used in memory systems with high bandwidth demands. PAM-3 signaling has advantages over NRZ and PAM-4, but compensation for ISI is necessary. While there have been many studies on FFE for NRZ and PAM-4 signals, research on PAM-3 FFE is lacking. In this paper, we propose a 2-tap FFE for a 30Gb/s PAM-3 transmitter and demonstrate its effectiveness in improving the eye-opening. Simulations in a channel environment with -6.02dB at 10GHz show that applying FFE increases both vertical and horizontal eye-opening. Further research on impedance matching is needed based on these results.
PVT 변동에 따라 나타나는 다양한 2T GC-eDRAM의 Data Retention 현상
이지원(Ji-won Lee),채주형(Joo-Hyung Chae) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
In this paper, the DRT characteristics are compared based on simulation considering the PVT variation of 2T GC-eDRAM. The proposed structure was analyzed for the characteristics commonly shown through a total of 144 overall simulations through Hspice. When the waveform is measured after giving the environment of the worst case in Hspice, the dominant current change and DRT are different for each characteristic. As a common conclusion to this, the conclusion that data loss at low supply voltage and temperature is slow is shown in the paper below.
저전력 VLSI SOC 최적화를 위한 3T_GC_eDRAM 분석
천현준(Hyeon-Jun Cheon),채주형(Joo-Hyung Chae) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
In this paper, we perform an analysis of existing 3T_GC_eDRAM cells (Conventional_3T, Boosted_3T, TG_3T) to determine the suitable cells for low-power VLSI SOC among 3T. Use comparison and analysis to select the best cell for implementing low-power VLSI SOC and explain why.
32Gb/s PAM-4 송신기 설계와 1-tap FFE 효과 분석
강수일(Su-Il Kang),강동우(Dong-Woo Kang),채주형(Joo-Hyung Chae) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
In this paper, a 32Gb/s PAM-4 transmitter is implemented to compare transmitter with 1-tap FFE or not. For full-rate operation in a highspeed environment, PAM-4 signaling was adopted instead of NRZ signaling. We also implement a 1-tap FFE to compensate for signal attenuation caused by the channel. It was simulated through Hspice on a CMOS 65nm process. To show the effect of FFE, a comparison was conducted through the Eye diagram of the final output terminal.