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도시형 친화형 저 풍속 적층 연곡형 풍력발전 시스템에 관한 연구
장미혜(Mi Hye Jang),정자춘(Jachu Jung) 대한전기학회 2010 대한전기학회 학술대회 논문집 Vol.2010 No.10
As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum faul coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.