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RISS 인기검색어
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- 저자 : 장준영 ( Juneyoung Jang ) (검색결과 3 건)
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장준영 ( Juneyoung Jang ),이제원 ( Jewon Lee ),권현우 ( Hyeunwoo Kwen ),서상호 ( Sang-ho Seo ),최평 ( Pyung Choi ),신장규 ( Jang-kyoo Shin ) 한국센서학회 2021 센서학회지 Vol.30 No.2
In this study, the sensitivity of an active pixel sensor (APS) was adjusted by employing a gate/body-tied (GBT) p-channel metal-oxide semiconductor field-effect transistor (PMOSFET)-type photodetector with a transfer gate. A GBT PMOSFET-type photodetector can amplify the photocurrent generated by light. Consequently, APSs that incorporate GBT PMOSFET-type photodetectors are more sensitive than those APSs that are based on p-n junctions. In this study, a transfer gate was added to the conventional GBT PMOSFET-type photodetector. Such a photodetector can adjust the sensitivity of the APS by controlling the amount of charge transmitted from the drain to the floating diffusion node according to the voltage of the transfer gate. The results obtained from conducted simulations and measurements corroborate that, the sensitivity of an APS, which incorporates a GBT PMOSFET-type photodetector with a built-in transfer gate, can be adjusted according to the voltage of the transfer gate. Furthermore, the chip was fabricated by employing the standard 0.35 μm complementary metal-oxide semiconductor (CMOS) technology, and the variable sensitivity of the APS was thereby experimentally verified.
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하드웨어 복잡도를 줄이기 위한 RDO내 DCT 공유구조의 HEVC 화면내 예측부호화기
이석호,장준영,변경진,엄낙웅,Lee, Sukho,Jang, Juneyoung,Byun, Kyungjun,Eum, Nakwoong 한국스마트미디어학회 2014 스마트미디어저널 Vol.3 No.4
HEVC 차세대 비디오 압축 표준은 ITU-TSG16 WP와 ISO/IEC JTC1/SC29, WG 11 두 단체 공동으로 2013년 표준화가 완료되었으며 기존 H.264 하이프로파일과 비교하여 압축효율은 두배 정도이다. HEVC에서 화면내 예측 (intra prediction) 모드는 planar와 DC 모드를 포함한 35개의 방향성 모드가 있으나 모든 모드를 적용한 부호화기를 구현하기 위해서는 하드웨어 복잡도가 증가하며 각 코딩유닛(coding unit) 사이즈에 따라 정확한 모드예측을 위한 RDO (rate distortion optimization) 계산에 필요한 DCT 사이즈도 증가하였기 때문에 본 논문에서는 하드웨어 사이즈를 줄이기 위하여 양자화를 위한 DCT와 SSE 계산을 위한 RDO 블럭내 DCT를 공유하는 화면내 예측부호기를 제안한다. 성능은 HEVC 참조소프트웨어인 HM-13.0과 비교하여 BD-rate는 평균 20% 증가하며 부호화시간은 4배 이상 단축되어 300MHz에서 FHD ($1920{\times}1080p$) 영상의 초당 60 프레임 실시간 부호화가 가능하다. HEVC is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264 high profile. Intra prediction has 35 directional modes including dc and planer. However an accurate mode decision on lots of modes with SSE is too costly to implement it with hardware. The key idea of this paper is a DCT shared architecture to reduce the complexity of HEVC intra encoder. It is to use same DCT block to quantize as well as to calculate SSE in RDO. The proposed intra encoder uses two step mode decision to lighten complexity with simplified RDO blocks and shares the transform resources. Its BD-rate increase is negligible at 20% on hardware aspect and the operating clock frequency is 300MHz@60fps on FHD ($1920{\times}1080$) image.
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Gate/Body-Tied 구조의 고감도 광검출기를 이용한 2500 fps 고속 바이너리 CMOS 이미지센서
김상환 ( Sang-hwan Kim ),권현우 ( Hyeunwoo Kwen ),장준영 ( Juneyoung Jang ),김영모 ( Young-mo Kim ),신장규 ( Jang-kyoo Shin ) 한국센서학회 2021 센서학회지 Vol.30 No.1
In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a highspeed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.
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