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캐패시터 부정합 보정 기능을 가진 8비트 스위치-캐패시터 사이클릭 D/A 변환기 설계
양상혁(Sang-Hyeok Yang),송지섭(Ji-Seop Song),김석기(Suki Kim),이계신(Kye-Shin Lee),이용민(Yong-Min Lee) 대한전기학회 2011 전기학회논문지 Vol.60 No.2
A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.