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3-Lavel PLA實現 및 EXCLUSIVE - OR셀 어레이 LAYOUT 硏究
文大哲(Dai Tdiue Moon) 호서대학교 사회과학연구소 1985 社會科學硏究 Vol.4 No.1
In this paper deal with the theoretical method of 3-level PLA and design of exclusive-OR array cell for 3-level PLA. Most PLA have constraints on minimal chip area and minimal input lines, thus the reduction of the number of product term in a sum of products expression is important in conventional random logic circuits. Also, this paper deals with lay out of Exclusive-ORArray using CHISEL language.