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Cho, Sunghun,Lee, DongSoo,Lee, Juri,Park, Hyung-Gu,Pu, YoungGun,Yoo, Sang-Sun,Hwang, Keum Cheol,Yang, Youngoo,Park, Cheon-Seok,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.3
This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.
Sunghun Cho,DongSoo Lee,Juri Lee,Hyung-Gu Park,YoungGun Pu,Sang-Sun Yoo,Keum Cheol Hwang,Youngoo Yang,Cheon-Seok Park,Kang?Yoon Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.3
This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using 0.13-μm CMOS technology and the die area is 4.2 mm². The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.