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A 15-GHz CMOS Multiphase Rotary Traveling-Wave Voltage-Controlled Oscillator
Zhang, Changchun,Wang, Zhigong,Zhao, Yan,Park, Sung-Min The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.3
This paper presents a 15-GHz multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-nm CMOS process, demonstrating the measured results of 2-GHz frequency tuning range, -11.3-dBm output power, -109.6-dBc/Hz phase noise at 1-MHz offset, and 2-ps RMS clock jitter at 15 GHz. The chip core occupies the area of $0.2mm^2$ and dissipates 12 mW from a single 1.2-V supply.
A 15 GHz, <tex> $-$</tex>182 dBc/Hz/mW FOM, Rotary Traveling Wave VCO in 90 nm CMOS
Changchun Zhang,Zhigong Wang,Yan Zhao,Sung Min Park THE INSTITUTE OF ELECTRICAL ENGINEERS 2012 IEEE Microwave and Wireless Components Letters Vol. No.
<P>This letter presents a phase-noise-centric design methodology of a rotary traveling wave voltage controlled oscillator (RTW VCO). Based upon this methodology, a 15 GHz multiphase RTW VCO is realized in a standard 90 nm CMOS process. Particularly, shielded coplanar striplines are exploited to provide better shielding protection and higher characteristic impedance with comparable Q-factor than conventional coupled transmission lines. Measured results of the proposed RTW VCO demonstrates the frequency tuning range of 2 GHz, the output power level of 11.3 dBm, the phase noise of 109.6 dBc/Hz at 1 MHz offset, the clock RMS jitter of 2 , and the power dissipation of 12 mW from a single 1.2-V supply. The chip core occupies the area of 0.2 .</P>
A 15-㎓ CMOS Multiphase Rotary Traveling-Wave Voltage-Controlled Oscillator
Changchun Zhang,Zhigong Wang,Yan Zhao,Sung Min Park 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.3
This paper presents a 15-㎓ multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-㎚ CMOS process, demonstrating the measured results of 2-㎓ frequency tuning range, -11.3-㏈m output power, -109.6-㏈c/㎐ phase noise at 1-㎒ offset, and 2-ps RMS clock jitter at 15 ㎓. The chip core occupies the area of 0.2 ㎟ and dissipates 12 ㎽ from a single 1.2-V supply.
Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Zhang, Changchun,Li, Ming,Wang, Zhigong,Yin, Kuiying,Deng, Qing,Guo, Yufeng,Cao, Zhengjun,Liu, Leilei The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Changchun Zhang,Ming Li,Zhigong Wang,Kuiying Yin,Qing Deng,Yufeng Guo,Zhengjun Cao,Leilei Liu 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and t재 fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18㎛ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.