http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Yike Zhang (검색결과 3 건)
- 무료
- 기관 내 무료
- 유료
-
Zhang, Peiyong,Fang, Haixia,Li, Yike,Feng, Chenhui The Korean Institute of Power Electronics 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.5
High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.
-
Peiyong Zhang,Haixia Fang,Yike Li,Chenhui Feng 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.5
High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.
-
Cheng Gui,Yike Zhang,Rui Jin,Yang Song,Rong Li,Yanjun Xing 한국섬유공학회 2021 Fibers and polymers Vol.22 No.4
Most previous work on the preparation of electrode materials has usually used to grind carbon nanofibers and addnon-reactive binders, which lead to limited surface area and lower electrochemical performance in electrode materials. In thisstudy, porous carbon nanofibers were prepared from non-miscible PAN/PVDF polymer blends by electrospinning andcarbonization to obtain electrode materials with high performance and high specific surface area. In the process of preparingelectrode materials, carbon nanofibers can be directly prepared as electrodes with high-performance and flexibility withoutadding any inactive materials, such as polymer binders or electronic conductors. Results showed that PF-C-50 has themaximum specific surface area of 773 m2 g-1 and the specific capacitance as high as 181 F/g at the current density of 0.4 A/gand 134 F/g at the current density of 1 A/g. PF-C-80 exhibits a specific capacitance as high as 156 F/g at the current densityof 0.4 A/g and 117 F/g at the current density of 1 A/g with the smallest IR drop and Rct. The prepared porous carbonnanofiber electrode improves the electrochemical performance and flexibility of the electrode material. These uniquestructures and characteristic materials can be excellent candidates for high-performance flexible electrodes, laying a goodfoundation for wearable devices.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
