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Study of HfO2 High-k Gate Oxide for Low-Temperature Poly-Si TFT
다까시노구찌,Jisim Jung,권장연,Seok Won Jeong,Seong Hoon Jeong,Wenxu XIANYU,노용한 한국물리학회 2006 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.48 No.I
We investigated HfO2/SiO2 thin film and found that it is a suitable candidate for an alternate gate insulator of SiO2 in thin film transistors (TFTs). Ultra thin SiO2 of 8.5 nm was deposited by inductively coupled plasma chemical vapor deposition (ICP CVD) below 200 C. Thin sputtered Hf metal films were oxidized and subsequently annealed under O2 and N2 ambient, respectively, to form polycrystalline HfO2 thin films simultaneously. We achieved a low leakage current level of 6.97 × 10.7 A/cm2 at .10 V and low EOT by HfO2/SiO2 double-layer structure.
Quantitative analysis of nano-defects in thin film encapsulation layer by Cu electrodeposition
Chu, Kunmo,Bae, Ki Deok,Song, Byong Gwon,Kim, Jaekwan,Park, Yong Young,Xianyu, Wenxu,Lee, Chang Seung,Sohn, Yoonchul Elsevier 2018 APPLIED SURFACE SCIENCE - Vol.453 No.-
<P><B>Abstract</B></P> <P>Thin-film encapsulation (TFE) is of great importance as a barrier film to protect organic devices and displays. A serious problem with the application of TFE is degradation of organic devices with penetration of oxygen and water vapor through pinholes having sub-micron size. Though many studies were tried to identify the pinholes, quantitative analysis of pinhole area has not been found yet. In this study, total pinhole area in TFE layer was quantitatively analyzed with the help of the Cu bumps electrodeposited on the pinholes. Empirical growth rate of the Cu bumps revealed that bump radius (r) and plating time (t) had a relationship of r<SUP>3</SUP> ∝ t. While size of the pinholes was deduced from starting point of Cu bump growth, number of the pinholes was extracted from size distribution of the Cu bumps. Unique feature of Cu bump morphology is also explained with a compositional analysis, demonstrating dissolution of Ni underlayer and its involvement in the formation of the Cu bumps.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Quantitative analysis of the pinholes in SiON thin film encapsulation is provided. </LI> <LI> Kinetic growth rate of electrodeposited Cu bumps on the pinholes was established. </LI> <LI> Pinhole size was deduced from the kinetic growth curve of the Cu bumps. </LI> <LI> Dissolved Ni underlayer involved in the formation of the Cu bumps. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>
Ultra Low Sheet Resistance on Poly Silicon Film by Excimer Laser Activation
다까시노구찌,Hyuck Lim,Do Young Kim,Hans S. Cho,Huaxiang Yin,권장연,Ji-Sim Jung,Jong-Man Kim,Kyung-Bae Park,Wenxu Xianyu,Xiaoxin Zhang 한국물리학회 2006 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.48 No.I
We found that the sheet resistance (Rs) value of phosphorus-doped poly-Si film activated by excimer laser annealing (ELA) has a strong correlation with the crystallinity in the film. At the optimum ELA condition of 10 shots and 450 mJ/cm2, we achieved a very low Rs value of 60 ohm/sq. in poly-Si films. With laser activation, we could get much lower Rs than with conventional rapid thermal annealing (RTA), for silicon layers of the same crystallinity level. The active dopant diffusion is observed from the energy which is speculated to correspond to the near-complete-melting energy regime during laser irradiation.
Ji Sim JUNG,Youngsoo PARK,Ji Sim JUNG,Do Young KIM,Hans S. CHO,Huasiang YIN,권장연,Kyung Bae PARK,Takashi NOGUCHI,Wenxu XIANYU 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.45 No.3
In this study, silicon dioxide (SiO2) lms were deposited at temperatures below 200C by using the inductivity coupled plasma chemical vapor deposition (ICP CVD) technique. The breakdown electric eld of as-deposited SiO2 lm by using this method shows values as high as 8.6 MV/cm. Additionally the eects of post-metallization annealing on SiO2 were investigated. After 400C annealing, the capacitance-voltage (C-V) characteristics such as at-band voltage, and interface trap density are improved considerably. In TFTs fabricated on single crystal SOI substrates at low temperatures below 400C by using this gate dielectric, a sharp gate voltage swing of 85 mV/dec. with high electron mobility was obtained. ICP CVD, by using high density plasma, can realize an excellent SiO2 lm and is expected to be applicable for the gate oxide in high performance Si TFT on plastic as well as on glass substrate.