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Thi Binh Nguyen Nguyen,Thi Kieu Diem Nguyen,Van Hue Trương,Thi Tuyet Ngoc Tran,van Bao Thang Phan,Thi Tuyen Nguyen,Hoang Bach Nguyen,Viet Quynh Tram Ngo,Van Tuan Mai,Paola Molicotti 질병관리본부 2023 Osong Public Health and Research Persptectives Vol.14 No.5
Objectives: Tuberculosis (TB) and drug-resistant TB (DR-TB) are national health burdens in Vietnam. In this study, we investigated the prevalence of rifampicin (RIF) and/or isoniazid (isonicotinic acid hydrazide, INH) resistance in patients with suspected TB, and applied appropriate techniques to help rapidly target DR-TB. Methods: In total, 1,547 clinical specimens were collected and cultured using the BACTEC MGIT system (Becton Dickinson and Co.). A resazurin microtiter assay (REMA) was used to determine the proportions of RIF and/or INH resistance. A real-time polymerase chain reaction panel with TaqMan probes was employed to identify the mutations of rpoB and katG associated with DR-TB in clinical isolates. Genotyping of the identified mutations was also performed. Results: A total of 468 Mycobacterium tuberculosis isolates were identified using the REMA. Of these isolates, 106 (22.6%) were found to be resistant to 1 or both antibiotics. Of the resistant isolates, 74 isolates (69.8%) were resistant to isoniazid (INH) only, while 1 isolate (0.94%) was resistant to RIF only. Notably, 31 isolates (29.24%) were resistant to both antibiotics. Of the 41 phenotypically INH-resistant isolates, 19 (46.3%) had the Ser315Thr mutation. There were 8 different rpoB mutations in 22 (68.8%) of the RIF-resistant isolates. The most frequently detected mutations were at codons 531 (37.5%), 526 (18.8%), and 516 (6.3%). Conclusion: To help prevent new cases of DR-TB in Vietnam, it is crucial to gain a comprehensive understanding of the genotypic DR-TB isolates.
Nguyen, Tram Thi Bao,Lee, Hanho The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.1
This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.
Tram Thi Bao Nguyen,Hanho Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.1
This paper presents a high-throughput lowcomplexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix 2<SUP>4</SUP>/2<SUP>3</SUP> FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.
High-efficiency Low-latency NTT Polynomial Multiplier for Ring-LWE Cryptography
Tuy Nguyen Tan,Tram Thi Bao Nguyen,Hanho Lee 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.2
This paper presents a novel architecture to perform polynomial multiplication in ring learning with errors (ring-LWE) cryptosystems. By employing number theoretic transform (NTT) of the input polynomials simultaneously, the multiplication latency is significantly reduced. In addition, a multiple-path delay feedback (MDF) architecture is used to speed up the multiplication process. As a result, the proposed NTT multiplier offers a better value of area-latency product compared with that of previous studies. The simulation results for the security parameters n = 512 and q = 12,289 on Xilinx Virtex-7 FPGA show that the proposed multiplier uses only about 8.69% of the number of clock cycles required by previous works to completely perform the polynomial multiplication. Furthermore, the obtained area-latency product value of the proposed architecture is less than 45.3% of that of previous works.
An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture
Sabooh Ajaz,Tram Thi Bao Nguyen,Hanho Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
This paper presents an area-efficient half-row pipelined layered low-density parity check (LDPC) decoder architecture for IEEE 802.11ad applications. The proposed decoder achieves a good tradeoff between throughput and area because of its ability to overcome the low-throughput bottleneck in conventional half-row decoders and the high-complexity bottleneck in fully parallel decoders. Synthesis results using TSMC 40 nm CMOS technology shows much better throughput at 10.84 Gbps and superior area efficiency, compared to previously reported LDPC decoders.