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Diagnosis of Delay Faults in the Presence of Clock Delays Considering Hazards
Yoshinobu Higami,Senling Wang,Hiroshi Takahashi,Shin-ya Kobayashi,Kewal K. Saluja 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
Presence of hazards can often lead to poor diagnosis. In this paper we propose a diagnosis method for gate delay faults in the presence of clock delays and hazards. Candidate faults are deduced using a fault dictionary which is created by the fault simulation considering hazard signals. Our diagnosis method can deduce candidate faults successfully even when a fault is activated by a hazard signal or when hazard signals are propagated to outputs, though conventional methods without considering hazards often fail to do so.