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Anıl Celebi,Sarp Erturk,Hyuk Jae Lee 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper presents an architecture design for low complexity motion estimation (ME) approaches. The bit-plane based modular structure of the proposed architecture is easily reconfigurable according to the ME method to be used. The comparatively high memory size required in previously proposed architectures is reduced by utilizing a 2D processing element (PE) architecture instead of a 1D systolic array architecture. The proposed architecture can reduce the memory size by up to 90% compared to low complexity ME hardware architectures proposed in the literature. Furthermore, the utilized memory architecture may reduce on chip memory bandwidth by about 85% compared to available low complexity ME hardware architectures by simply increasing the size of the utilized register array.