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Input Voltage/Current Input CMOS squaring Circuit
Chaiwat Sakul 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper proposes a voltage/current input CMOS squaring circuit. It consists of a mixed signal circuit and a basic squarer. Its major advantages over the other square are: this design can take two inputs (voltage input, current input) , its output can be the square of a voltage signal or the square of a current signal. Simulation results are carried by PSpice program. They find that the circuit can operate at ± 2 v power supplies, the voltage input range is ± 0.6 v , the current input range is ± 0.6 ㎂ , the current output range is 0-55 ㎂ and the -3 dB bandwidth is 31 ㎒.
A new CMOS squaring Circuit using Voltage/Current Input
Chaiwat Sakul 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper proposes a new CMOS squaring circuit using voltage/current input. It consists of a mixed signal circuit and a basic squarer. Its major advantages over the other square are: this design can take two inputs (voltage input, current input), its output can be the square of a voltage signal or the square of a current signal. Simulation results are carried by PSpice program. They find that the circuit can operate at ±2V power supplies, the voltage input range is ±0.6V, the current input range is ±0.6㎂, the current output range is 0.55㎂ ㎂ and the -3 ㏈ bandwidth is 31㎒.
A CMOS Square-Rooting Circuits
Chaiwat Sakul 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
The article proposes the square-rooting circuit. It bases the square-law characteristics of CMOS operating in saturation region for generating square-root function. The principle of the research is attained by the currentmirror circuit, which controls the voltages. The designed circuit dominates current as input and voltage as output. The structure of the circuit is simplified by only seven CMOS. Simulation results are demonstrated by PSpice program. They find that an input range is about 3㎂. whereas ±1.5_V supply voltage.
A single low-voltage CMOS analog multiplier
Chaiwat sakul,Ittipong Chaisayun 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A single low-supply CMOS Analog Multiplier based on MOS transistors operating in saturation is presented. The proposed circuit uses a single low-power supply. The proposed circuit consists of the multiplier cell, two voltage level shifters and two buffer circuits. The proposed multiplier was demonstrated by PSpice.
A versatile analog division circuit
Chaiwat Sakul,Somkiat Piangprantong,Kobchai Dejhan 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A versatile analog division circuit which is realized through the use of operational transconductance amplifier (OTA) is proposed in this paper. Its major advantages over the other analog divisions are : its output can be the division of two current signals, the division of two voltage signals, or the division of a current signal and a voltage signal. Therefore the proposed circuit can be applied more than conventional division circuits. Pspice simulation results are given to show Performance of the circuit.
A Mixed-Mode CMOS Square-Rooting Circuit
Chaiwat Sakul,Pumin Inpan,Kittikorn khanklaeo 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, a mixed mode square-rooting circuit based on CMOS transistors operating in saturation region is proposed. The major advantage over the other square-rooting circuits is that it has two inputs (voltage input Vi and current input Ii), and its output VO can be square-rooting function of either Vi or Ii. The input range is analyzed. Simulation results are carried out by PSpice program. They find that the circuit can operate at ± 2_V power supplies, the voltage input range is about 300㎷, the relative error as Ii=0_A and varied is 1.869% the current input range is about 100㎂, the relative error as Vi=0_V and varied is 1.865%, and the voltage output range is about 300㎷. Experimental results are done to confirm operation of the circuit by using CD4007 transistor arrays.
A CMOS Square-Law Vector Summation circuit
Chaiwat Sakul,Surin Kanchana 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
A CMOS vector summation circuit using the square-law characteristic of MOS transistors in saturation is presented. This circuit is widely used in communication, in order to analyze and processing the signal. The previous papers proposed to use the translinear of bipolar transistor, operational amplifier or current conveyor. The paper proposes to design the vector summation circuit by using MOS transistors and suitable for integrated circuit.
A low voltage supply four-quadrant analog multiplier circuit
Chaiwat Sakul 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
A four-quadrant analog multiplier circuit, for low voltage supply, is presented. Its advantages are as follow: it can be operating on low voltage supply, it can use either a single power supply or two power supplies, and all transistors used are the same dimension. Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation.