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RISS 인기검색어
- 검색키워드
- 저자 : Saad Arslan (검색결과 7 건)
- 무료
- 기관 내 무료
- 유료
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An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio
Arslan, Saad,Shah, Syed Asmat Ali,Lee, Jae-Jin,Kim, Hyungwon IEEE 2018 IEEE transactions on circuits and systems. a publi Vol.65 No.6
<P>Charging a capacitor array of a switched-capacitor (SC) dc-dc converter, supplying load circuits with a very short active period, can be pivotal to achieve high energy efficiency of its operation. This is because the capacitors may lose most of the stored energy during a long sleep period, and thus every sleep-to-active transition requires full recharging of the capacitors. In this brief, we present an energy efficient capacitor charging technique called split-capacitor charging, which charges a capacitor array in a step-wise fashion. Circuit simulations demonstrate that the proposed technique can reduce the energy wastage during sleep-to-active transition up to 66%. When tested on load circuits with a short active period, a voltage converter employing the proposed charging method shows up to 24% improvement in energy efficiency over conventional SC converters.</P>
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A Reconfigurable Controller for Testing On-Chip Voltage Converters
Saad Arslan,Syed Asmat Ali Shah,HyungWon Kim 대한전자공학회 2018 대한전자공학회 학술대회 Vol.2018 No.6
When testing on-chip voltage converters driving on chip loads, the use of external loads and control signal generation is not a feasible. External loads add unwanted parasitics while externally generated signals experience varying delays. To overcome these problems, on-chip reconfigurable control signal generation and load is needed. In this paper, a flexible on-chip controller is presented to test integrated voltage converters. The controller when accompanied by reconfigurable load circuit offers a comprehensive solution. Additionally, the controller is programmable through SPI for easy switching between test scenarios. Synopsys design platform is used for synthesis, Place and Route (PNR), and simulations. PNR simulations verify the controller"s SPI interface and control signal generation at 50 Hz clock frequency.
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Parallel Architecture of Concurrent ESP Engines for High-speed IPSec Routers
Saad Arslan,Hayotjan Aliev,HyungWon Kim 대한전자공학회 2018 대한전자공학회 학술대회 Vol.2018 No.11
Most encryption algorithms used in IPSec ESP have block dependance that restricts the encryption of incoming packet blocks in a pipeline fashion. To overcome this, the use of multiple ESP engines is employed in this paper. Thus, multiple packets are processed and encrypted in parallel. Also, the implemented IPSec engine incorporates a CAM based search engine as Security Association Database (SAD). The search engine provides three interfaces for searching, updating and creating entries. The design is verified using simulations and FPGA implementation at 100 MHz clock. Using four ESP engines, a throughput of 3.12 Gpbs is obtained. The measurements show almost linear increase in throughput with the increase in number of ESP blocks.
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혼성신호 컨볼루션 뉴럴 네트워크 가속기를 위한 저전력 ADC설계
이중연,말릭 수메르,사아드 아슬란,김형원,Lee, Jung Yeon,Asghar, Malik Summair,Arslan, Saad,Kim, HyungWon 한국정보통신학회 2021 한국정보통신학회논문지 Vol.25 No.11
본 논문은 저전력 뉴럴 네트워크 가속기 SOC를 위한 아날로그 Convolution Filter용 저전력 초소형 ADC 회로 및 칩 설계 기술을 소개한다. 대부분의 딥러닝의 학습과 추론을 할 수 있는 Convolution neural network accelerator는 디지털회로로 구현되고 있다. 이들은 수많은 곱셈기 및 덧셈기를 병렬 구조로 구현하며, 기존의 복잡한 곱셉기와 덧셈기의 디지털 구현 방식은 높은 전력소모와 큰 면적을 요구하는 문제점을 가지고 있다. 이 한계점을 극복하고자 본 연구는 디지털 Convolution filter circuit을 Analog multiplier와 Accumulator, ADC로 구성된 Analog Convolution Filter로 대체한다. 본 논문에서는 최소의 칩면적와 전력소모로 Analog Accumulator의 아날로그 결과 신호를 디지털 Feature 데이터로 변환하는 8-bit SAR ADC를 제안한다. 제안하는 ADC는 Capacitor Array의 모든 Capacitor branch에 Split capacitor를 삽입하여 모든 branch의 Capacitor 크기가 균등하게 Unit capacitor가 되도록 설계하여 칩면적을 최소화 한다. 또한 초소형 unit capacitor의 Voltage-dependent capacitance variation 문제점을 제거하기 Flipped Dual-Capacitor 회로를 제안한다. 제안하는 ADC를 TSMC CMOS 65nm 공정을 이용하여 설계하였으며, 전체 chip size는 1355.7㎛<sup>2</sup>, Power consumption은 2.6㎼, SNDR은 44.19dB, ENOB는 7.04bit의 성능을 달성하였다. This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛<sup>2</sup>, power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.
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High Speed Convolutional Neural Network Accelerator Based On Parallel Memory Access
Son, Hyun Wook · Lee, Dong Yeong · Mohammed E. Elbtity · Saad Arslan · Kim, Hyung Won 충북대학교 컴퓨터 정보통신 연구소 2008 컴퓨터정보통신연구 Vol.28 No.1
Convolutional Neural Networks (CNN) is an Artificial Intelligence (AI) algorithm that outperforms conventional ANNs for image processing applications. However, CNN requires significant computational resources and processing time, to analyze the characteristics of the image, using several convolutional filters and fully connected layers. In order to reduce the processing time, this paper proposes an ASIC CNN inference engine which exploits parallel hardware blocks and N-way Multiply and Accumulate (MAC) units. For verification, an extended MNIST dataset with 14 classes, which includes multiply/divide/add/subtract operators, is used. The hardware CNN engine achieves an accuracy of 93.5% with processing time as low as 116 us per 28x28 pixel image, implemented on Xilinx Zynq Ultrascale+ FPGA. Standard cell implementation using TSMC 180nm process occupies a core area of 7.56 mm2.
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Compact Spiking Neural Network Chip Design for Image Classification
Park, Dae Hu · Lee, Jung Yeon · Malik Summair Asghar · Hong Ji Un · Saad Arslan · Kim, Hyung Won 충북대학교 컴퓨터정보통신연구소 2008 컴퓨터정보통신연구 Vol.28 No.1
Deep learning using artificial neural networks in various fields has witnessed widespread acceptance because it outperforms other existing algorithms. However, it is not applicable to mobile environments with limited hardware resources due to power restrictions [1]. Therefore, the Spike Neural Network (SNN), which can mimic the human brain, has received great attention. In this work, we present a mixed signal circuit implementation of Spiking Neural network for a 3x3 image classification. The neural array, based on Leaky Integrate and Fire neural model along with synapse matrix is implemented in 130 nm CMOS technology. The verification of the neural network is performed by FPGA and Raspberrypi boards for successful classification of a 3x3 image.
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