http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Reza Sabbaghi-Nadooshan (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
-
Optimized QCA SRAM cell and array in nanoscale based on multiplexer with energy and cost analysis
Moein Kianpour,Reza Sabbaghi-Nadooshan,Majid Mohammadi,Behzad Ebrahimi Techno-Press 2023 Advances in nano research Vol.15 No.6
Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.
-
Mohsen Naeimi,Mohammd Bagher Tavakoli,Reza Sabbaghi-Nadooshan 국제구조공학회 2021 Smart Structures and Systems, An International Jou Vol.27 No.6
Power consumption has become the key constraint in electronics design, since the MOSFET threshold and hence the supply voltage can no longer be scaled. This trend calls for new device concepts such as Spintronic devices that are fundamentally different from CMOS. A carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid CNTFET-MTJ circuits; AND, XOR and 1-bit full adder. The proposed CNTFET-MTJ full adder design has 20 times lower Power-delay-product (PDP) compared to the previous CMOS- MTJ full adder. Also, the delay in CNTFET-MTJ circuit is reduced 20 times compared to the CMOS- MTJ circuit.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
