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A VLSI IMPLEMENTATION OF MPEG2 MOTION ESTIMATION ALGORITHM BASED ON MACROBLOCK CLUSTERING
Onoye,Takao,Takatsu,Masamichi,Fjita,Gen,Shirakawa,Isao,Matsumura,Kenji 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1
A new approach to the motion estimation is described dedicatedly for MPEG2 MP@HL moving pictures, which is based on the macroblock clustering. Adopting a two-level hierarchy in detecting motion vectors, the computational complexity is greatly reduced without degrading the quality of vectors. The result of motion detect simulation shows the clustering approach is practical enough for realtime encoding of HDTV level pictures. The proposed algorithm has been synthesized to a 2-D systolic array VLSI which contains 785K transistors, and occupies 102 ㎟ with a 0.6 ㎛ triple-metal CMOS technology.
VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding
Miyanohana, Koji,Fujita, Gen,Onoye, Takao,Shirakawa, Isao 대한전자공학회 1996 APCCAS:Asia Pacific Conference on Circuits And Sys Vol.1 No.1
A VLSI video encoder core is implemented dedicatedly for a very low bitrate coding, with the main theme focused on an edge detector and a vector quantizer. A new mechanism is devised so as to seek horizontal and vertical edges simultaneously, which can achieve a high throughput for the edge detector. A new scheme is also introduced into the PE (Processing Element) array so as to be shared by the vector quantizer and the motion estimator. Owing to these sophisticated concepts, specific functional macrocells have been implemented for the edge detector and vector quantizer in the total area of 55.3㎟ by a 0.6㎛ triple-metal CMOS technology.
SINGLE-CHIP IMPLEMENTATION OF MPEG2 DECODER DEDICATED TO MP@HL
Masaki,Toshihiro,Morimoto,Yasuo,Sato,Yoh,Onoye,Takao,Shirakawa,Isao 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1
A single-chip MPEG2 decoder dedicated to MP@HL is described, which consists of specific functional units, macroblock level pipeline buffers, and sequence controller. Owing to the sophisticated I/O interface facilities among functional units, macroblock level pipeline buffers are successfully incorporated with functional units. A new organization for frame memory and its interface is also devised. The designed decoder contains K transistors, and occupies 81.0㎟ with a 0.6㎛ triple-metal CMOS technology.