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Defect-Tolerant Design of a WSI FFT Processor
Tomabechi,Nobuhiro,Kanazawa,Shyouji 대한전자공학회 1997 ICVC : International Conference on VLSI and CAD Vol.5 No.1
This paper presents a defect-tolerant design of a wafer scale FFT processor in which special attention is paid to the chip area of the interconnection lines. It is indicated that an FFT processor whose chip area is 120 times that of the standard LSI with 50% yield may be realized with increased chip area of 6% and without decreasing the 50% yield.