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Time-Multiplexed 1687-Network for Test Cost Reduction
Ansari, Muhammad Adil,Jung, Jihun,Kim, Dooyoung,Park, Sungju IEEE 2018 IEEE transactions on computer-aided design of inte Vol.37 No.8
<P>The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.</P>
Time Division Multiplexing based Test Access for Stacked ICs
Muhammad Adil Ansari,Umair Saeed Solnagi,Jinuk Kim,Ahsin Murtaza Bughio,Sungju Park 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.1
The test cost and complexity of stacked ICs (SICs) are higher than those of 2D-ICs because an SIC is tested at more stages before shipping. The existing test access architectures and their optimization techniques for SICs underutilize the tester-channel frequency because the test data is shifted at low scan-shift frequency due to test power constrain. Moreover, the wafer-level test frequency is constrained by limited probe-pin to pad contact current; however, the package-level test can be performed at a higher frequency yet lower than the tester-channel frequency offered by the testers. Therefore, we present a time-multiplexed test access architecture for SICs that leverages the tester-channel frequency at both the wafer-level and package-level tests. Unlike exiting architectures, the proposed architecture does not require the knowledge of the number of dies to be stacked and the hierarchical tier of each die. The proposed architecture is discussed for SICs based on IEEE standards 1149.1 and 1500. The experimental results with a synthetic SIC, constructed with ITC’02 benchmark SoCs, show significant reduction in the test time. Furthermore, the analyses based on the test frequency limits and the number of stacked dies show that the proposed architecture scales well with increasing frequency limits and the number of stacked dies.
On Diagnosing the Aging Level of Automotive Semiconductor Devices
Jung, Jihun,Ansari, Muhammad Adil,Kim, Dooyoung,Yi, Hyunbean,Park, Sungju IEEE 2017 IEEE Transactions on Circuits and Systems II: Expr Vol. No.
<P>Semiconductor aging is a serious threat to the reliability of a system. We address the aging level of semiconductor components by describing the degree of semiconductor aging under certain operating conditions, including voltage, frequency, temperature, and usage rate. Aging level information can be used to follow the real aging rate of a device, predict the remaining life, and control the device performance under certain degradation conditions by balancing the operation of various device components. Such applications can improve the reliability of automotive semiconductor systems, which should have longer lives than mobile systems. In this brief, we present an aging level estimating flip-flop (FF) that can be used for these and other applications as well. Moreover, we can control the operation of the proposed FF by controlling its clock and control signals. We demonstrate an application of the proposed FF for aging-monitoring, showing that, by halting the operation of the proposed FF, the power consumption is significantly reduced compared with other approaches.</P>
Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells
Jihun Jung,Muhammad Adil Ansari,Dooyoung Kim,Sungju Park 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.2
The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.
Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells
Jung, Jihun,Ansari, Muhammad Adil,Kim, Dooyoung,Park, Sungju The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.2
The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.