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On-Chip Spiral Inductors and On-Chip Spiral Transistors for Accurate Numerical Modeling
M. Dhamodaran,R. Praveen Kumar,S. Jegadeesan 한국자기학회 2018 Journal of Magnetics Vol.23 No.1
This paper presents a new model for designing on-chip spiral inductor and on-chip spiral transistors. For this, the coupling between on-chip inductors and transistors has been implemented. The electromagnetic coupling between the inductors and the transistors and the mutual inductance are modeled by presenting the magnetic vector potential to study the coupling effect. It changes the surface integral of the magnetic field into the loop integral of the magnetic vector potential to calculate the coupling. In this method, the partial mutual inductance idea to compute the mutual inductance between two conductor sections instead of conductor loops can be developed. The inductance classification is applied to an on-chip environment to characterize interconnects and integrated inductors. The investigative model is reconsidered to incorporate the semiconductor substrate losses and the skin effect. The numerical solutions of the investigative model are also presented. To simulate the proposed model ADS Momentum software is used.
S. Jegadeesan,M. Dhamodaran,M. Azees,S. Sri Shanmugapriya 한국자기학회 2018 Journal of Magnetics Vol.23 No.2
In this paper, a high resolution magnetic measurements are performed in an AES (advanced encryption standard) cryptographic FPGA by using a newly designed magnetic probe. The probe consists of high resolution scanning system and magnetic field collecting coil integrated with 3-stage low noise amplifier to enhance the sensed voltage. Also, to improve the performance of the magnetic coil, the Si-substrate is removed under the coil by using FIB process. The results and discussion section clearly shows that, the proposed magnetic probe gives more detailed information about the susceptible area of an AES cryptographic FPGA surface with high resolution maps in different frequency bands compared with the existing magnetic probe.
Terahertz Micro-Strip Patch Antenna Design and Modelling for 6G Mobile Communication
Jeyakumar P.,Anandpushparaj J.,Thanapal P.,Meenatchi S.,Dhamodaran M. 대한전기학회 2023 Journal of Electrical Engineering & Technology Vol.18 No.3
The future mobile communication networks are emerging drastically and research is being pursued all around the world. To match with the increasing demand for high-speed data communication, wide bandwidth and a high gain antenna are required. Therefore, in this work, the frequency above 100 GHz is chosen as it provides high bandwidth and also suitable for short range communication. Initially, we have designed an antenna with carrier frequency of 300 GHz by comparing it with three different patch materials like Copper, Graphene and Gold and the antenna parameters are analysed. The obtained result shows that the graphene patch has a return loss of −27.70 dB, maximum bandwidth of 10.4 GHz and ideal radiation efficiency of 98.38%. Then the link budget evaluation for the target data rate is 100 Gbps at the bandwidth of 30 GHz on 10 m link distance is analyzed for mobile communication. By executing link budget evaluations in terms of code rate, target SNR, path loss and number of antenna elements required are validated. Finally, the proposed link budget is verified for various modulation schemes using MATLAB.