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Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs
Ansari, M. Adil,Kim, Dooyoung,Jung, Jihun,Park, Sungju The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.1
Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.
Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs
M. Adil Ansari,Dooyoung Kim,Jihun Jung,Sungju Park 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.1
Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.
Dooyoung Kim,M. Adil Ansari,Jihun Jung,Sungju Park 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5
Various test data compression techniques have been developed to reduce the test costs of system–on–a–chips. In this paper, a scan chain reordering algorithm for code–based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS ’89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.
Kim, Dooyoung,Ansari, M. Adil,Jung, Jihun,Park, Sungju The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.5
Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.
Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function
Dooyoung Kim,M. Adil Ansari,Jihun Jung,Jinuk Kim,Sungju Park 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.2
Scan flip-flop based physically unclonable function (SCAN-PUF) has been proposed to protect integrated circuits (ICs) from security threats such as unauthorized access and IC cloning. In this paper, we propose an efficient SCAN-PUF technique that improves the uniqueness of responses with low cost overhead. The proposed SCAN-PUF first determines an optimal number of power-up state observations and then selects scan flip-flops as the PUF elements (P-ELEMENTs) through a given number of observations. A Bayesian model is adopted to evaluate the reliability of the P-ELEMENTs, and a grouped PELEMENT selection method is introduced to obtain more P-ELEMENTs than a predetermined threshold. To evaluate the proposed SCAN-PUF, we observed the power-up states of scan flip-flops from 15 chips fabricated using the 65-nm CMOS technology. The optimal number of observations is determined according to the reliability of the P-ELEMENTs, and the reliability, randomness, and uniqueness of the responses are then analyzed.