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AUTOMATION AND OPTIMIZATION OF TEST APPLICATION FOR JTAG-BASED DESIGNS
Castrodale, Grant L.,Ghazale, Silvio E. Bou,Kanopoulos, Nick 대한전자공학회 1989 ICVC : International Conference on VLSI and CAD Vol.1 No.1
The Joint Test Action Group JTAG has proposed a standard test interface based on boundary scan which gives serial access to the components on a board. Due to the serial nature of boundary scan, the time it takes to apply test vectors increases tremendously over the traditional in-circuit testing. We propose techniques for applying the vectors to reduce the test application time. Analytical expressions for the application time of each of the techniques are derived based on the connectivity of the chips, the length of the test vectors of each chip, and the I/O pin count and location within the boundary scan path. These formulas are used to determine which technique to use for the automatic translation of chip-level sets to a board-level test set. Since the boundary scan interface is being standardized, it becomes possible to provide automatic vector translation and optimization of test application for any board designed according to the standard.