http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Kyungchol Huh (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
-
Design and verification of On-Chip Debug Unit for 32bit RISC core
Hyeongbae Park,Kyungchol Huh,Taehoon Kim,Changwon Ryu,Seungpyo Jung,Jusung Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper introduces the basic concept of processor debug and the design and verification procedure of OCDU ( On-Chip Debug Unit), which is designed for 32 bit RISC processor, ARM7 core. OCDU consists of TAP(Test Access Port) that generates the control signals for debugging logic, ICE(In Circuit Emulator) monitoring the operation of the processor, and 3 scan chains. After OCDU and ARM7 core are merged to one designed and implemented with FPGA, the verification of the design is carried out through device recognition, carrying-out instructions of JTAG(Joint Test Action Group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting breakpoints and watch points.
-
A processor with an improved ARM7 core and peripherals
Hyunwoo Cho,Kyungchol Huh,Seungwon Song,Taehoon Kim,WonTae Choi,Haksun Kim,Jusung Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper is about designing RISC Processor which is compatible with ARM7 and has partial functions improved and added. The existing ARM7 Processor designed with a latch-based pipeline structure has a problem of time violation at the back-end. Also, its built-in 32 x 8-bit multiplier requires many cycles. In order to solve these problems of the ARM7 Processor, in this study, a flip-flop-based pipeline structure was designed, and in the aspect of (calculation time) x (number of gates), a 32x16 multiplier which is superior to the existing one was designed. Additionally, the new processor includes AMBA BUS, Audio codec interface, MMU (Memory Management Unit), and 192Kbyte RAM. After FPGA test was performed on the designed processor, a chip was fabricated with 0.18 ㎛ CMOS processing. Through application program tests such as unit instruction test, instruction combination test, ADPCM(Adaptive Differential Pulse Code Modulation), SOLA(synchronized-overlap-add), MP3 decoder, it was confirmed that the fabricated chip is compatible with ARM7TDMI. Furthermore, it was confirmed that the designed 32-bit RISC Processor performs all application programs in the unit of MIPS (million instructions per second), which is much better than the previous processor.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
