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Storage Logic Primitives Based on Stacked Memristor-CMOS Technology
Cho, Sung-Wan,Eshraghian, Jason,Eom, Ju-Song,Kim, Sungjin,Cho, Kyoungrok American Scientific Publishers 2016 Journal of Nanoscience and Nanotechnology Vol.16 No.12
<P>A newer and higher standard of circuits is emerging with the advent of memristive logic components. In the present paper memristor-CMOS (MCM)-based storage primitives are presented by exploiting the resistive switching property of the memristor. Practical implementation and fabrication of MCM-based logic circuits were verified by way of SPICE modeling, related simulations, and device characterization. The logic structure was designed by combining memristors with CMOS, and fabrication was performed by atomic layer deposition and an aluminum evaporation process in the form of a memristor on 350-nm CMOS technology. The proposed design method realized more efficient area utilization compared with current CMOS technology. As a result, the presented memristor-CMOS-based SR flip-flop and JK master slave flip-flop decreased the area by a factor of 31.2-52.2% with respect to the equivalent state memory CMOS circuits. The proposed memristor-CMOS technology allows for significant reduction of the silicon area, sustainability of Moore's law, and can be applied to increase the density of microchips.</P>
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture
Kyoungrok Cho,Sang-Jin Lee,Kavehei, Omid,Eshraghian, Kamran IEEE 2014 IEEE transactions on very large scale integration Vol.22 No.7
<P>This paper presents a CMOS image sensor (CIS) VLSI architecture based on a single-inverter time-to-threshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposable medical cameras and on-chip autonomous wireless security vision systems. A 64 × 64 pixel array was fabricated using standard 130-nm CMOS process consuming only 5.9 nW/pixel with integration time of 2 ms at +0.5 V supply. The high fill factor of 58% facilitated a better SNR at a low supply voltage when compared with other CIS architectures. The pixel has a dynamic range of 54 dB with 7.8 frame per second.</P>
Signal Flow Platform for Mapping and Simulation of Vertebrate Retina for Sensor Systems
Cho, Kyoungrok,Baek, Seungbum,Cho, Sung-Wan,Kim, Jun-Ho,Goo, Yong Sook,Eshraghian, Jason K.,Iannella, Nicolangelo,Eshraghian, Kamran IEEE 2016 IEEE SENSORS JOURNAL Vol.16 No.15
<P>Our visual processing system is remarkably good; the retina is nothing like the CMOS image sensor, or for that matter, any of the vision processing architectures that have driven vision systems research for over three decades. Therefore, before embarking upon the complex task of architectural mapping of the retina into hardware, it is essential to gain a realistic insight into the theoretical functions of the retina. In addition, an understanding of the kinds of chemical/electrical interactions taking place must be ascertained in order to venture into the next insurmountable task - the simulation platform. This paper presents a generic signal flow architecture for the mapping of the vertebrate retina derived from ionic current movements and interactions. The approach pursued is focused on the functional behavior of the signal that traverses from the photoreceptor to the ganglion cell in the architecture through transforming the system of nonlinear ordinary differential equations (ODEs) into an equivalent set of non-linear integral equations to cope with the singularity characteristic of retinal systems, providing an increase in the computational speed of similar to 36% when compared with the conventional ODE methods, thus enhancing the realization of a functional retina as part of future hardware-based sensor systems.</P>
이경록(Kyoungrok Lee),조영탁(Youngtag Cho) 육군사관학교 화랑대연구소 2021 한국군사학논집 Vol.77 No.3
Vision is a concept that commonly refers to goal, value, ideology, etc. that organizations pursue in the long run. Vision is different from the strategy for it only presents a blueprint without any detailed action plan to implement. In addition, realization of the Vision is more important than planning of it which makes it difference from dream and hope. An upright vision should be armed with perfection in terms of attributes, condition, and components of the vision. Above all, vision must be established through the participation of all members. In 2019, the Republic of the Korea Army published 「ROK Army Vision 2050」as a guiding principle that the future ROK Army should pursue in coming 30 years. The purpose of this study is to identify supplementary points of the ROK Army Vision 2050 at academic level, and to present a standard model that can be used widely for the entire level of the ROK Army who has to design their own vision. This study suggests the process of visioning in 4 stages: forecasting the change of future trend, assessing the current state of the organization, setting the vision, and future outcome of each sector. The ROK Army Vision provides direction of each planning document and logical basis. The significant contribution of this study is that it has presented a standard model of vision design process which can be utilized by all echelons in the ROK Army.
Seok-Man Kim,Hoshin Cho,Minho Nam,Seong-Gon Choi,Kyoungrok Cho IEEE 2015 Journal of display technology Vol.11 No.1
<P>Touch screen panel (TSP) technology has dramatically enhanced the connectivity between man and machine, in particular within mobile consumer electronics where mobility is a key design criterion. This paper introduces a novel charge-sensing technique derived from the behavioral characteristics of a mutual capacitive touch screen panel. The approach is based on a reduced scan algorithm whereby both the target and its surroundings form the node and the selection process is conducted in two phases. In the first phase, the introduction of a charge on the TSP is sensed, while the second phase evaluates when the touch event occurs on the TSP. The proposed algorithm reduces the number of sensing nodes activated during the waiting period by observing the behavior of a single row within the charge sensing array, as opposed to the more conventional approach in which all TSP nodes are scanned. As a result, power consumption is reduced by 60% during the sensing phase, while the dynamic sensing range is increased by a factor of 38% for a complete two-stage sensing cycle.</P>
Neuromorphic Vision Hybrid RRAM-CMOS Architecture
Eshraghian, Jason Kamran,Cho, Kyoungrok,Zheng, Ciyan,Nam, Minho,Iu, Herbert Ho-Ching,Lei, Wen,Eshraghian, Kamran IEEE 2018 IEEE transactions on very large scale integration Vol.26 No.12
<P>The development of a bioinspired image sensor, which can match the functionality of the vertebrate retina, has provided new opportunities for vision systems and processing through the realization of new architectures. Research in both retinal cellular systems and nanodriven memristive technology has made a challenging arena more accessible to emulate features of the retina that are closer to biological systems. This paper synthesizes the signal flow path of photocurrent throughout a retina in a scalable 180-nm CMOS technology, which initiates at a <TEX>$128\times 128$</TEX> active pixel image sensor, and converges to a <TEX>$16\times 16$</TEX> array, where each node emits a spike train synonymous to the function of the retinal ganglionic output cell. This signal can be sent to the visual cortex for image interpretation as part of an artificial vision system. Layers of memristive networks are used to emulate the functions of horizontal and amacrine cells in the retina, which average and converge signals. The resulting image matches biologically verified results within an error margin of 6% and exhibits the following features of the retina: lateral inhibition, asynchronous adaptation, and a low-dynamic-range integration active pixel sensor to perceive a high-dynamic-range scene.</P>