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A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor
Sewook Hwang,Kyeong-Min Kim,Jungmoon Kim,Seon Wook Kim,Chulwoo Kim IEEE 2013 IEEE transactions on very large scale integration Vol.21 No.3
<P>This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5× to 8× of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-μm CMOS process occupies an active area of 0.27 mm<SUP>2</SUP> and consumes 15.56 mA.</P>
Kim Sewook 단국대학교 한문교육연구소 2021 International Han-character Education Research Vol.4 No.1
인간은 문장이나 담화에서 이동, 운율적 강조 등의 방법으로 진리 조건적인 의미를 바꾸지 않으면서도 청자에게 효과적으로 전달하기 위해 정보를 구조화한다. 교사가 표현하는 한자의 ‘형음의’의 담화 구조도 신・구 정보적 특징을 지닌 분절된 정보가 될 수 있다. 실제로 이 ‘X는 Y이다’라는 판단구는 교수자, 학습자의 낭독 과정 속에서 충분히 발생한다. 이에 본고는 한자의 형음의를 제시하는 구조를 3 가지로 분류했다. 각각 ①식(예 : 靑 청 푸르다), ②식(예 : 靑 푸르다 청), ③식(예 : 靑 푸를 청)으로 개괄하고 이 3가지 구조 방식에 의사소통역량과 파도 모형이론을 적용하여 정보량 차이의 존재 여부를 살피고 각 식의 기능적 측면에서 접근했다. ①식(예 : 靑 청 푸르다)은 뜻에 중점을 둔 구조로 특히 오른쪽에 열린 공간을 통해서 의미를 더 자세히 제시할 수 있는 구조로 한문의 독해에 유용한 구조이고, ②식 (靑 :푸르다 청)은 언어 생활에서의 활용을 강조하되, 문장 독해 학습에도 중점을 둔 구조로 주로 교수자들이 선호한 구조이다. ③식은 수식어‧중심어의 단순한 통사구조를 통해 학생들이 뜻을 쉽게 이해하고, 口誦을 쉽게 할 수 있는 구조로 언어생활에서 사용되는 음이 강조된 구조이 고 한자서의 音義의 설명에 유용한 구조이다. 이를 통해 한자의 형음의를 표현한 순서와 방법의 차이에 따라 전달하는 의미에 차이가 있을 수 있어 이에 해당하는 적당한 방법을 모색하는 것이 필요하고 한문 교육과 관련된 한자의 형음의를 표시하는 데에는 구습을 답습하지 않고 목표와 성격에 따라 합당한 구조의 모색을 강조했다. Humans structure information to effectively convey to listeners without changing the meaning of truth conditions by means of movement or rhyme emphasis in sentences or discourse. The discourse structure expressed by teachers can also be segmented with new and old information. In fact, this phrase ‘X is Y’ occurs sufficiently in the reading process of instructors and learners. Accordingly, this paper classified the structure of explaining shape, meaning, sound of Ham-characters in high school textbook(漢文Ⅰ) in three categories. Each was outlined in type ① (靑 청 푸르다), type ② (靑 푸르다 청), and type ③ (靑 푸를 청). The above three structural type are studied by applying communication dynamism and wave theory to see if there is any functional difference of information. Type ① (靑 청 푸르다) is focused on reading comprehension, especially can present various meanings through an open space on the right. Type ② (靑 푸르다 청) emphasizes the sound in language life, also focuses on reading comprehension like type ①. Type ③ is focused on easily reading aloud for student through a simple syntactic structure, therefore emphasizes the sound in language life. If the order of shape, meaning, sound in Han-characters is different, the meaning of the information may be different. This paper emphasized the search for a reasonable order of shape, meaning, sound in Han-characters according to each goals in high school textbook.
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier
Kim, Ja-Young,Song, Junyoung,You, Jungtaek,Hwang, Sewook,Bae, Sang-Geun,Kim, Chulwoo IEEE 2017 IEEE transactions on circuits and systems. a publi Vol.64 No.6
<P>This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm(2) in a 65-nm CMOS technology.</P>
Sewook Hwang,Jabeom Koo,Kisoo Kim,Hokyu Lee,Chulwoo Kim IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.9
<P>This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 <SUP>°</SUP>C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5<SUP>°</SUP>C over a temperature range of 0<SUP>°</SUP>C ~ 110<SUP>°</SUP>C. The entire block occupies 0.008 mm<SUP>2</SUP> in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s.</P>
확장가능한 다목적 주문형 멀티미디어 시스템의 설계 및 구현
김태현(Taehyoun Kim),조진성(Jinsung Cho),성민영(Minyoung Sung),정세욱(Sewook Jung),김기한(Keehan Kim),신현식(Heonshik Shin) 한국정보과학회 1997 한국정보과학회 학술발표논문집 Vol.24 No.2Ⅲ
주문형 멀티미디어 시스템은 사용자의 요구에 따라 다양한 응용을 가지며, 이러한 응용에 대해 서비스를 제공하는 서버는 고객의 수에 따라 융통성 있게 확장될 수 있어야 한다. 본 논문에서는 사용자의 목적에 적합한 멀티미디어 응용 프로그램의 작성을 용이하도록 하는 다목적 고객 API와 통신망의 형태와 사용자의 규모에 따라 적절히 구축될 수 있는 분산 다중 서버 시스템을 설계, 구현한다. 설계된 분산 다중 서버는 전위 노드의 역할을 수행하는 서비스 조정자와 복수의 데이타 서버로 이루어진 서버풀(pool)로 구성되며, 유닉스 호환의 플랫폼에 쉽게 이식, 확장될 수 있도록 설계, 구현되었다. 또한 구현된 프로토타입 서버 시스템과 고객 API를 이용하여 작성된 CinemaNet 응용 프로그램을 연동하여 WWW 환경에서 주문형 비디오 서비스를 개발한다.
Mucibacter soli gen. nov., sp. nov., a new member of the family Chitinophagaceae producing mucin
Min-Kyeong Kim,Sewook Park,Tae-Su Kim,Yochan Joung,Ji-Hye Han,SEUNG BUM KIM 한국미생물학회 2019 The journal of microbiology Vol.57 No.5
A Gram-stain-negative, mucus-forming, motile by gliding, non-spore-forming and short rod-shaped bacterial strain designated R1-15T was isolated from soil and its taxonomic position was evaluated using a polyphasic approach. Strain R1-15T grew at 15–37°C (optimum, 30°C), at pH 6–7 (optimum, pH 6) and in the presence of 0–1% (w/v) NaCl (optimum, 0%) on 0.1X TSA. On the basis of 16S rRNA gene sequence similarity, the novel strain was assigned to the family Chitinophagaceae of the phylum Bacteroidetes, and its closest related taxa were species of the genera Taibaiella (88.76– 90.02% sequence similarity), Lacibacter (89.24–90.00%), Chitinophaga (88.61–89.76%), and Terrimonas (89.04%). Flexirubin- type pigments were produced. The only isoprenoid quinone was MK-7, and the major polar lipid was phosphatidylethanolamine. Based on whole genome comparisons between the strain R1-15T and the type strains of relatives, the orthologous average nucleotide identity values were 66.9– 67.0%. The DNA G+C content of strain R1-15T was 43.8 mol%. The combination of phylogenetic, chemotaxonomic and phenotypic data clearly supported separation of strain R1-15T from related taxa, and thus the name Mucibacter soli gen. nov., sp. nov. is proposed. The type strain is R1-15T (= KCTC 62274T = JCM 31190T).
Validation of Methods Based on PCR for the Detection of GM Events in South Korea
Young Rae Cho,Min Ki Shin,Eun-ju Song,Jun Hyun Sung,Younjeong Han,Min Young Bae,Ji Hyun Yoo,Sunmi Kim,Jyongeun Myung,Jisoo Hong,Sewook Park,Chohee Kim,Dongmi Choi,Mee Kyung Kim 한국식품영양과학회 2019 한국식품영양과학회 학술대회발표집 Vol.2019 No.10
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile
Sewook Hwang,Minyoung Song,Young-Ho Kwak,Inhwa Jung,Chulwoo Kim IEEE 2012 IEEE journal of solid-state circuits Vol.47 No.5
<P>A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH ΔΣ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of ±0.5% to 3.5% in steps of 0.5% and three modulation frequencies of <I>f</I><SUB>m</SUB>, 2 <I>f</I><SUB>m</SUB> and 3 <I>f</I><SUB>m</SUB>. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm<SUP>2</SUP> in a 0.13-μm CMOS process and consuming 23.72 mW at 3.5 GHz.</P>