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Theoretical and Experimental Investigation of Graphene/High- <tex> $\kappa $</tex>/p-Si Junctions
Jaewoo Shim,Gwangwe Yoo,Dong-Ho Kang,Woo-Shik Jung,Young-Chul Byun,Hyoungsub Kim,Won Tae Kang,Woo Jong Yu,Hyun-Yong Yu,Yongkook Park,Jin-Hong Park IEEE 2016 IEEE electron device letters Vol.37 No.1
<P>Here, we theoretically and experimentally investigate the impact of a high-kappa layer inserted between graphene and p-Si in a graphene/Si junction. We have achieved 86-fold and 222-fold reductions in a specific contact resistivity (rho(c)) by inserting 1-nm-thick Al2O3 and 2-nm-thick TiO2 in the graphene-semiconductor junction, respectively, corresponding to lowering the effective barrier height by 0.24 and 0.12 eV. Furthermore, we propose a graphene-induced gap state model that simultaneously considers the graphene's modulation by a gate bias and the effect of the high-kappa insertion.</P>
The Effects of a Thermal Recovery Process in In-Ga-Zn-O (IGZO) Thin Films Transistor
Park, Hyung-Youl,Yoo, Gwangwe,Lee, Hanjae,Lim, Myung-Hoon,Baek, Jung Woo,Choi, Changhwan,Park, Jin-Hong American Scientific Publishers 2016 Journal of Nanoscience and Nanotechnology Vol.16 No.11
<P>In this paper, we demonstrated the effect of titanium (Ti) diffusion and modulation of interface traps by carrying out an annealing process on In-Ga-Zn-O (IGZO). The effect of diffused Ti atoms from the source/drain (S/D) electrodes was systematically investigated through secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, HSC chemistry simulation, and electrical measurements. Higher concentrations of Ti and oxygen vacancies were observed with increasing annealing temperature. In addition, we demonstrated that the electrical stability of the IGZO thin films transistors (TFTs) was enhanced by a second thermal annealing process performed at temperature 50 degrees C lower than the first annealing step to diffuse Ti atoms in the lateral direction with minimal effects on the channel conductivity. As a result, we obtained a threshold voltage shift (Delta V-TH) of only 2.9 V after the first annealing step at 300 degrees C for 1 hour and a second annealing step at 250 degrees C for 3 hours with a channel length of 4 mu m.</P>
Gwang-Sik Kim,Gwangwe Yoo,Yujin Seo,Seung-Hwan Kim,Karam Cho,Byung Jin Cho,Changhwan Shin,Jin-Hong Park,Hyun-Yong Yu IEEE 2016 IEEE electron device letters Vol.37 No.6
<P>The effect of post-deposition H<SUB>2</SUB> annealing (PDHA) on the reduction of a contact resistance by the metal-interlayer-semiconductor (M-I-S) source/drain (S/D) structure of the germanium (Ge) n-channel field-effect transistor (FET) is demonstrated in this letter. The M-I-S structure reduces the contact resistance of the metal/n-type Ge (n-Ge) contact by alleviating the Fermi-level pinning (FLP). In addition, the PDHA induces interlayer doping and interface controlling effects that result in a reduction of the tunneling resistance and the series resistance regarding the interlayer and an alleviation of the FLP, respectively. A specific contact resistivity (p<SUB>c</SUB>) of 3.4×10<SUP>-4</SUP>Ω·cm<SUP>2</SUP> was achieved on a moderately doped n-Ge substrate (1×10<SUP>17</SUP> cm<SUP>-3</SUP>), whereby 5900× reduction was exhibited from the Ti/n-Ge structure, and a 10× reduction was achieved from the Ti/Ar plasma-treated TiO<SUB>2-x</SUB>/n-Ge structure. The PDHA technique is, therefore, presented as a promising S/D contact technique for the development of the Ge n-channel FET, as it can further lower the contact resistance of the M-I-S structure.</P>
Germanium p-i-n avalanche photodetector fabricated by point defect healing process.
Shim, Jaewoo,Kang, Dong-Ho,Yoo, Gwangwe,Hong, Seong-Taek,Jung, Woo-Shik,Kuh, Bong Jin,Lee, Beomsuk,Shin, Dongjae,Ha, Kyoungho,Kim, Gwang Sik,Yu, Hyun-Yong,Baek, Jungwoo,Park, Jin-Hong Optical Society of America 2014 Optics letters Vol.39 No.14
<P>In this Letter, we report Ge p-i-n avalanche photodetectors (APD) with low dark current (sub 1 μA below V(R)=5??V), low operating voltage (avalanche breakdown voltage=8-13??V), and high multiplication gain (440-680) by exploiting a point defect healing method (between 600C and 650C) and optimizing the doping concentration of the intrinsic region (p-type ~101? cm?3). In addition, Raman spectroscopy and electrochemical capacitance voltage analyses were performed to investigate the junction interfaces in more detail. This successful demonstration of Ge p-i-n APD with low dark current, low operating voltage, and high gain is promising for low-power and high-sensitivity Ge PD applications.</P>
Jeon, Jaeho,Jang, Sung Kyu,Jeon, Su Min,Yoo, Gwangwe,Park, Jin-Hong,Lee, Sungjoo IEEE 2015 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.14 No.2
<P>We report that control over the grain size and lateral growth of monolayer MoS2 film, yielding a uniform large-area monolayer MoS2 film, can be achieved by submitting the SiO2 surfaces of the substrates to oxygen plasma treatment and modulating substrate temperature in chemical vapor deposition (CVD) process. Scanning electron microscopy and atomic force microscopy images and Raman spectra revealed that the MoS2 lateral growth could be controlled by the surface treatment conditions and process temperatures. Moreover, the obtained monolayer MoS2 films showed excellent scalable uniformity covering a centimeter-scale SiO2/Si substrates, which was confirmed with Raman and photoluminescence mapping studies. Transmission electron microscopy measurements revealed that the MoS2 film of the monolayer was largely single crystalline in nature. Back-gate field effect transistors based on a CVD-grown uniform monolayer MoS2 film showed a good current on/off ratio of similar to 10(6) and a field effect mobility of 7.23 cm(2)/V.s. Our new approach to growing MoS2 films is anticipated to advance studies of MoS2 or other transition metal dichalcogenide material growth mechanisms and to facilitate the mass production of uniform high-quality MoS2 films for the commercialization of a variety of applications.</P>