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Gain Based Delay Balancing in the Deep Submicron Era
Ryusuke EGAWA,Jubee TADA,Hiroaki KOBAYASHI,Gensuke GOTO 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper presents a novel technique to balance the delays in a combinational logic circuit for an equal delay circuit design. The delay balancing technique relies on a gain based delay model and the availability of a continuous size delay elements library. Based on the concept of logical effort in very large scale integrated circuits in the deep submicron era, our proposed technique attempts to minimize a delay difference of combinational logic circuits. Delay balancing tools based on our proposal are developed, and the effectiveness of tools is evaluated. Experimental results show that our proposal achieves 9.96% delay variations on average in combinational logic circuits.
Gain-based Delay Balancing Technique for Wave Pipelining
Jubee Tada,Ryusuke Egawa,Keiichiro Sano,Gensuke Goto,Tadao Nakamura 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, we propose a delay balancing technique for wave pipelining. Wave pipelining is expected to resolve some problems in a conventional pipeline and achieve a higher frequency circuit. However, realizing wave pipelining requires high efficient delay balancing technique. To resolve this problem, we propose a delay balancing technique based on gain-based delay model for wave pipelining. Experimental results show that our approach can achieve up to 6 times throughput by increasing 23% transistors.