http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch
An, Tai-ji,Cho, Young-Sea,Park, Jun-Sang,Ahn, Gil-Cho,Lee, Seung-Hoon The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.5
This work proposes a two-channel T-I 10b 160 MS/s asynchronous pipelined-SAR ADC minimizing offset and gain mismatches between channels without any calibration. Each channel of the proposed ADC is based on a two-stage pipelined-SAR topology, where the first and second stage determines 4b and 7b, respectively, for high conversion rate and low power. An asynchronous SAR algorithm removes on-chip high-speed clock generators for SAR operation, while a simple detection circuit solves a meta-stability problem of the comparator commonly observed in asynchronous SAR ADCs. Analog circuits such as comparators and residue amplifiers are shared to capacity between two channels to reduce various channel mismatches limiting the linearity of the T-I ADC. Three separate reference voltage drivers for two SAR ADCs and a residue amplifier prevent lots of undesirable disturbance among reference voltages due to each different switching operation. The prototype ADC in a 28 nm CMOS process demonstrates a measured differential and integral non-linearity within 0.71 LSB and 0.70 LSB at 10b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 51.43 dB and 62.01 dB at 160 MS/s, respectively. The proposed ADC occupies an active die area of $0.23mm^2$ and consumes 3.5 mW at a 1.0 V supply voltage.
An, Tai-Ji,Hwang, Moon-Sang,Choe, Won-Jun,Ahn, Gil-Cho,Lee, Seung-Hoon IEEE 2018 IEEE Transactions on Circuits and Systems I: Regul Vol.65 No.10
<P>This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is shared among multi channels. The dual-sampling architecture for the output amplifiers also reduces the power consumption of the column driver IC, where the operating time of the time-shared DAC and the output amplifier is efficiently handled during the limited 1-horizontal time. The sampling accuracy of the dual-sampling architecture is improved by a simple dummy switch and a source follower. The proposed time-shared DAC with the dual sampling is implemented by a 0.13- <TEX>$\mu \text{m}$</TEX> high-voltage complementary metal-oxide-semiconductor process and integrated in a 960-channel column driver IC, while the effective channel area of the column driver IC is 5520 <TEX>$\mu \text{m}^{2}$</TEX>. As a result of driving an 11-inch-wide quad extended graphics array AMOLED panel by using the prototype column driver IC, the panel uniformly generates a clear image.</P>
A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch
Tai-ji An,Young-Sea Cho,Jun-Sang Park,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.5
This work proposes a two-channel T-I 10b 160 MS/s asynchronous pipelined-SAR ADC minimizing offset and gain mismatches between channels without any calibration. Each channel of the proposed ADC is based on a two-stage pipelined-SAR topology, where the first and second stage determines 4b and 7b, respectively, for high conversion rate and low power. An asynchronous SAR algorithm removes on-chip high-speed clock generators for SAR operation, while a simple detection circuit solves a meta-stability problem of the comparator commonly observed in asynchronous SAR ADCs. Analog circuits such as comparators and residue amplifiers are shared to capacity between two channels to reduce various channel mismatches limiting the linearity of the T-I ADC. Three separate reference voltage drivers for two SAR ADCs and a residue amplifier prevent lots of undesirable disturbance among reference voltages due to each different switching operation. The prototype ADC in a 28 nm CMOS process demonstrates a measured differential and integral nonlinearity within 0.71 LSB and 0.70 LSB at 10b, respectively, with a maximum signal-to-noise-anddistortion ratio and a spurious-free dynamic range of 51.43 dB and 62.01 dB at 160 MS/s, respectively. The proposed ADC occupies an active die area of 0.23 ㎟ and consumes 3.5 mW at a 1.0 V supply voltage.
An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme
Jae-Hyuk Lee,Jun-Ho Boo,Jun-Sang Park,Tai-Ji An,Hee-Wook Shin,Young-Jae Cho,Michael Choi,Jin-Wook Burm,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.2
This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm2. The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.
Tai-Ji An,Gil-Cho Ahn,Seung-Hoon Lee IET 2016 IET power electronics Vol.9 No.3
<P>This study presents a high-efficiency low-noise pulse-width modulation (PWM) DC-DC buck converter based on multi-partition switching for mobile system-on-a-chip applications. A multi-partition switching technique is employed for the control of large current driving switches to minimise the switching noise. In addition, a PWM control with a switching frequency of 2 MHz is applied for the driving of output stage with a heavy load to optimise the power efficiency. The prototype DC-DC buck converter with an active die area of 0.28 mm(2) was implemented using a 0.18 mu m bipolar-CMOS-DMOS (BCD) process. The peak power efficiency is 93%, while supplying an output current of 200 mA and an output voltage of 1.8 V.</P>
A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs
Jun-Sang Park,Tai-Ji An,Suk-Hee Cho,Yong-Min Kim,Gil-Cho Ahn,Ji-Hyun Roh,Mun-Kyo Lee,Sun-Phil Nah,Seung-Hoon Lee 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.2
This work proposes a 12b 100 MS/s 0.11 μm CMOS three-step hybrid pipeline ADC for highspeed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dualchannel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 μm CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm² and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.
A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs
Park, Jun-Sang,An, Tai-Ji,Cho, Suk-Hee,Kim, Yong-Min,Ahn, Gil-Cho,Roh, Ji-Hyun,Lee, Mun-Kyo,Nah, Sun-Phil,Lee, Seung-Hoon The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.2
This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.
Ho-Jin Kim,Jun-Ho Boo,Jae-Hyuk Lee,Jun-Sang Park,Tai-Ji An,Sung-Han Do,Young-Jae Cho,Michael Choi,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.6
This paper proposes a calibrated 14-bit 10 MS/s 28 nm CMOS Nyquist successive-approximation register (SAR) analog-to-digital converter (ADC). The upper 9 bits and the remaining lower 5 bits are determined, respectively, using a binary-weighted capacitor array and segmented reference voltages divided from a simple resistor string. While the proposed calibration is applied only to the critical most significant 4-bit capacitors, the segmented reference voltages to decide the lower 5 bits are reused via a unit capacitor. This creates a small weight on the calibration digital-to-analog converter (DAC) in place of making an adjustment to the small-sized actual capacitor value. The proposed calibration does not require extra capacitors smaller than the unit capacitor, reducing the chip area and circuit complexity. The comparator employs a noise-reduction capacitor, enabling it to realize low-noise performance with low-power. The prototype ADC in a 28 nm CMOS occupies an active die area of 0.062 ㎟ and consumes 351 μW at a 1.0 V supply voltage. After calibration, the prototype ADC shows a measured differential non-linearity (DNL) and integral non-linearity (INL) within 1.59 LSB and 2.92 LSB, respectively, at 14 bits with a maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 70.0 dB and 85.0 dB at 10 MS/s, respectively.
Area-efficient Ramp Signal-based Column Driving Technique for AMOLED Panels
Tai-Ji An,Moon-Sang Hwang,Won-Jun Choe,Jun-Sang Park,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.4
This work proposes a ramp signal-based column driving technique to maximize the area efficiency of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED) panels. The proposed column driving technique replaces the 2<SUP>n</SUP> reference voltages coming from the conventional n-bit resistor digital-to-analog converters (RDAC) with a single ramp signal, thereby reducing the area of the column driver IC by 44.3%. A weighted two-step interpolation structure, composed of the first-stage 6-bit ramp signal and the second-stage 2-bit amplifier DAC, reduces the required operation speed of the ramp signal under a limited 1-horizontal (1-H) time, while processing 8-bit image signals. The performance of the proposed column driving technique is verified with a 96-channel prototype IC fabricated in a 0.18 μm CMOS process. The deviation of voltage output (DVO) of the prototype IC are within ±6 mV, and the unit channel area is 4200 μ㎡.