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Analog Delay Locked Loop with Wide Locking Range
Yoo, Changsik The Institute of Electronics and Information Engin 2001 Journal of semiconductor technology and science Vol.1 No.3
For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.
Fermi Level Pinning at Electrical Metal Contacts of Monolayer Molybdenum Dichalcogenides
Kim, Changsik,Moon, Inyong,Lee, Daeyeong,Choi, Min Sup,Ahmed, Faisal,Nam, Seunggeol,Cho, Yeonchoo,Shin, Hyeon-Jin,Park, Seongjun,Yoo, Won Jong American Chemical Society 2017 ACS NANO Vol.11 No.2
<P>Electrical metal contacts to two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) are found to be the key bottleneck to the realization of high device performance due to strong Fermi level pinning and high contact resistances (R-c). Until now, Fermi level pinning of monolayer TMDCs has been reported only theoretically, although that of bulk TMDCs has been reported experimentally. Here, we report the experimental study on Fermi level pinning of monolayer MoS2 and MoTe2 by interpreting the thermionic emission results. We also quantitatively compared our results with the theoretical simulation results of the monolayer structure as well as the experimental results of the bulk structure. We measured the pinning factor S to be 0.11 and -0.07 for monolayer MoS2 and MoTe2, respectively, suggesting a much stronger Fermi level pinning effect, a Schottky barrier height (SBH) lower than that by theoretical prediction, and interestingly similar pinning energy levels between monolayer and bulk MoS2. Our results further imply that metal work functions have very little influence on contact properties of 2D-material-based devices. Moreover, we found that Re is exponentially proportional to SBH, and thee processing parameters can be controlled sensitively upon chemical doping into the 2D materials. These findings provide a practical guideline for depinning Fermi level at the 2D interfaces so that polarity control of TMDC-based semiconductors can be achieved efficiently.</P>
Metallic contact induced van der Waals gap in a MoS2 FET
Kim, Changsik,Lee, Kwang Young,Moon, Inyong,Issarapanacheewin, Sudarat,Yoo, Won Jong The Royal Society of Chemistry 2019 Nanoscale Vol.11 No.39
<P>Electrical metal contacts formed with 2D materials strongly affect device performance. Here, we used scanning transmission electron microscopy (STEM) and energy-dispersive spectroscopy (EDS) to characterize the interfacial structure formed and physical damage induced between MoS2 and the most commonly used metals, Ti, Cr, Au, and Pd. We further correlated the electrical performance with physical defects observed at the 2D interfacial structure. The contact resistances were higher in the order of Ti, Au, Pd, and Cr contacts, but all 4-point probe mobilities measured with metals in contact with identical quadrilayer MoS2 were ∼65 cm<SUP>2</SUP> V<SUP>−1</SUP> s<SUP>−1</SUP>, confirming the reliability of the devices. According to the STEM and EDS analyses, the Ti contact gave rise to a van der Waals gap between the clean quadrilayer MoS2 and the Ti contact. By contrast, Cr migrated into MoS2 while Mo and S counter-migrated into the SiO2 substrate. Au and Pd formed glassy layers that resulted in the migration of Mo and S into the Au and Pd electrodes. These interfacial structures between MoS2 and contact metals strongly correlated with the electrical performance of 2D MoS2 FETs, providing practical guidelines to form van der Waals contacts.</P>
A HDMI-to-MHL Video Format Conversion System-on-Chip (SoC) for Mobile Applications
Hyochang Kim,Changsik Yoo 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.4
The high-definition multimedia interface (HDMI) output of the application processor (AP) of a mobile handset is converted to a mobile highdefinition link (MHL) signal by a video format conversion system-on-chip (SoC). The MHL signal is then delivered over a 5-pin cable to a television (TV) or monitor, allowing the audio/video (AV) contents of a mobile handset to be displayed on a large screen. The functionalities and performance of the HDMI-to- MHL video format conversion SoC implemented in a 130-nm CMOS technology have been verified by the compliance tests specified by the HDMI and MHL standards.
A 12-Gb/s Continuous-time Linear Equalizer with Offset Canceller
Baekjin Lim,Changsik Yoo 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.2
A DC-offset of a continuous-time linear equalizer (CTLE) is cancelled by an analog offset canceller (OFC). The bandwidth (BW) of the OFC is designed to be 10-㎑ not to affect the received signal integrity. The BW of the OFC set by an active-RC integrator is lowered by increasing the effective resistance through pulse width modulation (PWM). The input offset of the OFC itself is removed by employing chopping technique. The offset-cancelled CTLE is applied to a four-channel 12-Gb/s wireline receiver compliant with thehigh-definition multimedia interface (HDMI) version 2.1 standard. The 12-Gb/s wireline receiver has been implemented in a 28-㎚ CMOS process. The eye opening for the bit-error rate (BER) smaller than 10<SUP>-12</SUP> becomes larger than 0.26 unit-interval (UI) with the OFC while the BER is always larger than 10<SUP>-12</SUP> without the OFC.
Younghoon Kim,Changsik Yoo IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.61 No.6
<P>A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11-μm CMOS process with a 0.127-mm<SUP>2</SUP> active silicon area. The TDADC consumes 1.7 μW from a 0.6-V supply voltage.</P>
Macro-Model of Magnetic Tunnel Junction for STT-MRAM including Dynamic Behavior
Kyungmin Kim,Changsik Yoo 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.6
Macro-model of magnetic tunnel junction (MTJ) for spin transfer torque magnetic random access memory (STT-MRAM) has been developed. The macro-model can describe the dynamic behavior such as the state change of MTJ as a function of the pulse width of driving current and voltage. The statistical behavior has been included in the model to represent the variation of the MTJ characteristic due to process variation. The macro-model has been developed in Verilog-A.
A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport
Kyungyoul Min,Changsik Yoo IEEE 2010 IEEE transactions on consumer electronics Vol.56 No.4
<P>A clock and data recovery (CDR) for the physical layer of DisplayPort at sink side is described. A 1/5-rate linear phase detector (PD) compares the phase of the incoming data with that of sampling clock to recover a clean clock and data. A pattern based frequency detector (PBFD) reduces frequency error to be in the pullin-range of the 1/5-rate linear PD. The PBFD reduces the frequency error down to 3.2% before the linear PD starts its operation. The CDR implemented in a 0.13 m CMOS process shows 29-ps rms and 154-ps peak-to-peak jitter in the recovered clock and 10<SUP>-7</SUP> bit error rate (BER) for 2<SUP>31</SUP>-1 pseudorandom binary-sequence (PRBS) input while consuming 87mW from a 1.2-V supply.</P>